VHDL one clock pulse in 0.5sec

[hardware_guy]

Hello. Please help me with this VHDL code.

I need to get pulse, with duration of one clock cycle, in every exact period of time.

For example, my oscillator is 50MHz, I have counter in my system ,signal "count".
To get one clk in every 0.5sec, I use this code:

pulse <= '1' when ( count= X"17D7840" or count= X"2FAF080" or count= X"47868C0" or count= X"5F5E100" or count= X"7735940" or count= X"8F0D180") else '0';

But this is very clumsy solution, and I need to write all combinations.
I know, I can also use counter, what will be reset after every 0.5sec, for this, but I just what to learn a better way.

I think there should be more elegant formula or something..
Something, what will not require extra reseteble counter.

I want one clock cycle pulse every 0.5sec, for 10 sec after reset event. How to do this without writing 20 times "count= X" " and without using extra resetable counter ?

Please advice.

 

[KlausST]

Hi,

Use a 25 bit wide counter.
Count from 0....24 999 999, then use synchronous reset to start the counter with 0 again.

Klaus

 

[hardware_guy]

Thanks Klaus, but as I said, I was thinking to find a solution, what will not require extra resetable counter. My main counter is deeply integrated in the system, it is halted sometimes, resets in some situations. If I will create extra counter, I will need to keep in mind that extra counter all the time, and sync all control signals to it. One day I can forget about it, and will get glitch, what will take me hours to troubleshoot. I was just thinking, if there is a way, how I can tell VHDL something like pulse <= '1' when ( count ?can be divided to X"17D7840"?

 

[ads-ee]

You can only do a modulo if the integrated counter you are using actually rolls over at a multiple of the 0.5sec, otherwise you'll have a "glich" regardless. Besides that if that integrated counter you are using starts and stops then it won't have a 0.5sec interval all the time.

So which do you want, a 0.5sec pulse every time, or a random interval pulse based on whether the integrated counter happened to stop and restart? Seems like you've got a built in design flaw.

Also if you think your going to "forget" about your accurate 0.5sec pulse generator and end up with a glitch that takes hours to troubleshoot means you probably aren't documenting your design enough using a header with a module description and good comments throughout the code (ones that say why you are doing something and not what the lines of code are doing).

 

[vGoodtimes]

First, 25000000 is not a power of two.

Another way to do this is to have a free-running counter "freeCount" that starts at 0 and a terminal condition "termCount" that can also start at 25000000. When freeCount == termCount, output a pulse and set termCount = termCount + 25000000.

This would mean that anything stopping freeCount from counting would also delay/stop the output pulses. Likewise, resetting freeCount would require resetting termCount to 25000000. This method strongly couples freeCount and this output pulse and has these weird behaviors that could stop the pulse from occurring twice per second.