vhdl: logical and of two vectors of std_logic_vector type

[saur]

I've two vectors and I want to perform logical and on them:
eg

...........
mod_ins : IN STD_LOGIC_VECTOR(7 downto 0);
........
signal mod_ena_sig : STD_LOGIC_VECTOR(7 downto 0);
............
if(mod_ins = mod_ins and mod_ena_sig) then
......

It seems to say there is some error in the if statement. Can't figure out what the error is.

Awaiting all the suggestions.
Thanks
Saur

 

[FvM]

Instead of unnecessary brackets around the if expression, you'll want it around (mod_ins and mod_ena_sig) to clarify the operator precedence.

I presume you would find the answer yourself by reading the error message thoroughly. It's a bit more specific than saying "some error".