[SOLVED] VHDL incomplete if statements in clocked processes

[fmaximovic]

Hi all,

one of the biggest caveats about VHDL concerns incomplete "if" statements, since they need some "else" clause to prevent the formation of latches (which are bad, I guess). However, incomplete "if" statements are those that open clocked processes, like

if (CLK'event and CLK='1') then
...
end if;

since they do not comprise any "else" clauses.
I imagine my question is trivial but I can't find an explanation: why can "if" statements be incomplete in clocked processes? Does this hold true for any "if" statement inside a clocked process, included those regarding signals other than "CLK"?

Thank you in advance




I see there is a similar thread here
https://www.edaboard.com/threads/265262/
but I was wondering whether there was the chance to gather some more details/interpretations.
Again, thanks

 

[TrickyDicky]

its because a clocked process describes a d-type flipflop. So at the clock level, it would be illegal to have an else in line with the clock.

But inside the clock branch, like I said in the other thread, if statements just equate to clock enables.

 

[fmaximovic]

thanks trickydicky, that's what i was searching