VHDL, if statements and timing delay?

[journeyman200]

Hello everyone,

I'm pretty new to VHDL was hoping you guys could give me some advice. I'm writing a state machine code on my DE2 board where every time I press a button it will an output will change between 3 states. Each state will display either 1,2, or 5 on a BCD. However after I press the button, it will consecutively display every state. Sometimes the BCD will display garbage. I have if statements to prevent more than one change at a time. However once I slowed down the 27MHZ clock to around a second, its working better, but damn slow. Is this just a timing issue or coding? Any other way to delay it ? What's the reason for the garbage BCD outputs? I notice it sometimes happens when I first turn on my board as well. Thanks in advance.

ENTITY voltdisplaysetting IS

PORT (

			clock_slow			: IN STD_LOGIC; --- Active low
			reset				: IN STD_LOGIC; --- Active low
			volt_switch			: IN STD_LOGIC;

	
			voltBCD1_display	: OUT STD_LOGIC_VECTOR(6 downto 0);
			Volt_setting		: OUT STD_LOGIC_VECTOR(2 downto 0)
	);
			
END;


ARCHITECTURE algorithm OF voltdisplaysetting is 



	--- Seven segment codes, 0 is on (for DE2)
	CONSTANT	ONE			:	STD_LOGIC_VECTOR(6 downto 0):= "1111001";
	CONSTANT	TWO			:	STD_LOGIC_VECTOR(6 downto 0):= "0100100";
	CONSTANT	FIVE		:	STD_LOGIC_VECTOR(6 downto 0):= "0010010";
	CONSTANT	MAX			:	STD_LOGIC_VECTOR(25 downto 0):= "01111111111111111111111111";
	
	SIGNAL volt_state		:	STD_LOGIC_VECTOR(6 downto 0):= "1111001";
	SIGNAL volt_next 		:	STD_LOGIC_VECTOR(6 downto 0):= "1111001";
	SIGNAL timer			:   STD_LOGIC_VECTOR(25 downto 0):= "00000000000000000000000000";

	

	
		
BEGIN
	--- State memory
	PROCESS(clock_slow, reset, volt_next)
	
	BEGIN
		IF( reset = '0') THEN
			volt_state <= ONE;

		ELSIF( rising_edge(clock_slow) ) THEN
			IF (timer >= MAX) THEN
			volt_state <= volt_next;
			timer <= "00000000000000000000000000";
			ELSE
				timer <= timer + '1';
			END IF;
			
		END IF;
				
	END PROCESS;
	

	PROCESS (volt_state, volt_switch, reset)
		VARIABLE stop_temp: STD_LOGIC:='0'; --prevents more than one state change during same switch state.
	BEGIN

		
		IF ((volt_switch = '1') AND (stop_temp = '1')) THEN
			
			IF (volt_state = ONE)  THEN
			volt_next <= TWO;
			stop_temp := '0';
			

	
			ELSIF (volt_state = TWO)  THEN
			volt_next <= FIVE;
			stop_temp := '0';



			ELSIF (volt_state = FIVE) THEN
			volt_next <= ONE;
			stop_temp := '0';
	
			
			END IF;
			
			
		ELSIF (volt_switch = '0') THEN
			stop_temp := '1';
			
		END	IF;
		
		IF (reset = '0') THEN
			volt_next <= ONE;
		END IF;
	
			voltbcd1_display <=volt_state;
		
	END PROCESS;
	

END;

 

[FvM]

It's not a VHDL problem, just a logical one. Your logic demands the state to be advanced while the button is pressed. You are apparently expecting a state change, when the button is pressed a new. In other words, you need to detect the button state change. This can be done best by comparing previous and present button state. You need to oberve, that the event must be set for exactly one clock period of the state machine, in other words, it must use the same clock respectively clock enable.

The edge detect logic can run at full clock speed, if the switch input is debounced. Otherwise it has to be reduced to a reasonable scan speed of e.g. 15 to 50 Hz.

SIGNAL volt_switch_prev: STD_LOGIC;
SIGNAL volt_switch_event: STD_LOGIC;
...
IF rising_edge(clock) THEN
  volt_switch_prev <= volt_switch;
  volt_switch_event <= volt_switch AND NOT volt_switch_prev; 
END IF;