VHDL frequency counter

[Codeman]

vhdl counter

Hi,

I need to implement a simple VHDL frequency counter for a school project. Must be 4 multiplexed digits. (the FPGA as few macrocells).

I know how to implement the counter and the BCD to seven segment. is the multiplexing and puting things togheter that i need help.

Can anyone point me to an example? Must be very simple.

Thank you in advance.

Codeman

 

[Marcel Majoor]

vhdl frequency counter

For the multiplexing you need a 0..3 counter, and based on this counter value you output the correct data.
The counter is a free-running 2 bit counter.
I assume that the actual output has already be detertmined in 4 8-bit registers.

entity .... is
  port(
    FREQIN: in  std_logic;
    7SEG  : out std_logic_vector(7 downto 0);
    DIGITS: out std_logic_vectot(3 downto 0);
  );
end ....


signal frequencyin     : std_logic;
signal 7segoutputDigit0: std_logic_vector(7 downto 0);
signal 7segoutputDigit1: std_logic_vector(7 downto 0);
signal 7segoutputDigit2: std_logic_vector(7 downto 0);
signal 7segoutputDigit3: std_logic_vector(7 downto 0);

signal counter  : std_logic_vector(1 downto 0);
signal digiton  : std_logic_vector(3 downto 0);
signal output   : std_logic_vector(7 downto 0);



.... frequency measurement code
.... measured frequency -> BCD
---- BCD -> 7segment (7segoutputDigitx)



-- This clock should be a clock that has the frequency of the multiplexing
-- rate. If every digital has to be 'refreshed' 100 times as second then
-- this clock should be 400 hz (4 outputs...)
process (muxclk)
begin
  if rising_edge(muxclk)
    counter <= counter + 1;
  end if;
end process;


-- 7 segment output
output <= 7segoutputDigit0 when (counter = "00)
                           else
          7segoutputDigit1 when (counter = "01)
                           else
          7segoutputDigit2 when (counter = "10)
                           else
          7segoutputDigit3 when (counter = "11);


-- The multiplexer output is probably also needed 'externally' so
-- the hardware knows were 'output' should go to.
-- In case we need individual outputs for the multiplexer
digiton(0) <= '1' when (counter = "00")
                  else
              '0';
digiton(1) <= '1' when (counter = "01")
                  else
              '0';
digiton(2) <= '1' when (counter = "10")
                  else
              '0';
digiton(3) <= '1' when (counter = "11")
                  else
              '0';



-- The 'real' inputs/outputs
-- Always a good idea to work 'internally' with signals and then pass them
-- on to the actual inputs/outputs. This allows easy conversion when inverted
-- inputs/outputs are used. Internally we then always work with high level ('1')
-- active signals ...
DIGITS      <= digiton;
7SEG        <= output;
frequencyin <= FREQIN;

If I were to take on a project as yours I would make individual components of (for example):
. clock generation (frequency clock / mux clock)
. frequency counting
. counted frequency to BCD conversion
. BCD to 7 segment conversion
. Output mux

Each component can then be tested individually using a test bench.
The 'main' application would then nothing more than a unit that instantiates the components and connects the components to the actual hardware.

 

[Codeman]

frequency counter vhdl

Hi Marcel,

Thanks for your awnser.

Please check your PM

 

[ramesh.palasa]

hello sir ,
i'm doing project on frequency counter for 16 bit disply
components
clock generation (frequency clock / mux clock)
. 16 bit counter
latches
and gate
. counted frequency to BCD conversion
. BCD to 7 segment conversion

and i want VHDL code for clock generation
plz post
thankq

 

[vipinlal]

@ramesh : for bcd to 7 segment conversion see this link :
https://vhdlguru.blogspot.com/2010/03/vhdl-code-for-bcd-to-7-segment-display.html
for counter program see this link:
https://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
for clock generation use the following code snippet:
clk_period <= 1 ns; --period of clk;
clk_process rocess
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

The above code is not synthesizable.

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