DNA5511
Newbie level 3
Hi, so i did this program for a vending machine, the machine works fine, but i get this error, and i cant find whats wrong, this project is duw tomorrow , can some help me plz.
The errors i got:
The top level of the design:
i cant find , or understand whats wrong
The errors i got:
#Error: ELAB1_0008: reu.vhd : (369, 15): Cannot read output : "Sie1".
# Error: ELAB1_0008: reu.vhd : (370, 16): Cannot read output : "Sie2".
# Error: ELAB1_0008: reu.vhd : (371, 16): Cannot read output : "Sie3".
# Error: ELAB1_0008: reu.vhd : (372, 16): Cannot read output : "Sie4".
The top level of the design:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cafe_pf is Port ( inicio: in std_logic; rst: in std_logic; ck: in std_logic; Unp: in std_logic; DoP: in std_logic; Ci5: in std_logic; DiP: in std_logic; Sie1: out std_logic_vector(3 downto 0); Sie2: out std_logic_vector(3 downto 0); Sie3: out std_logic_vector(3 downto 0) ; Sie4: out std_logic_vector(3 downto 0) ); end cafe_pf; architecture behavioral of cafe_pf is type nombres_estados is (Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18); signal estado: nombres_estados; signal entrada_aux: std_logic_vector (3 downto 0); component clk200Hz Port ( clk_in : in STD_LOGIC; reset : in STD_LOGIC; clk_out: out STD_LOGIC ); end component; component conta1 port( x : std_logic; clk: in std_logic; rst : std_logic; y: out std_logic); end component; component Seg7 port( x : in std_logic_vector(3 downto 0); display : out std_logic_vector(6 downto 0) ); end component; signal ck2: std_logic; signal Unp1: std_logic; signal DoP2: std_logic; signal Ci52: std_logic; signal DiP2: std_logic; signal Sie11: std_logic_vector(0 to 6); signal Sie21: std_logic_vector(0 to 6); signal Sie31: std_logic_vector(0 to 6); signal Sie41: std_logic_vector(0 to 6); signal Sie1_i: std_logic_vector(3 downto 0); signal Sie1_i1: std_logic_vector(3 downto 0); signal Sie1_i2: std_logic_vector(3 downto 0); signal Sie1_i3: std_logic_vector(3 downto 0); begin cl: clk200hz port map(ck,rst,ck2); pulso_unpeso: conta1 port map(Unp,ck2,rst,Unp1) ; pulso_dospesos: conta1 port map(DoP,ck,rst,DoP2) ; pulso_cincopesos: conta1 port map(Ci5,ck,rst,Ci52) ; pulso_Diezpesos: conta1 port map(Dip,ck,rst,DiP2) ; entrada_aux<=DiP2&Ci52&DoP2&Unp1; process(inicio, ck2) begin if rst='1' and ck2'event then estado<=Q0; end if; if inicio='1' then estado<=Q0; elsif ck2='1' and ck2'event then case estado is when Q0 => case entrada_aux is when "0000" => estado<=Q0; when "0001" => estado<=Q1; when "0010" => estado<=Q2; when "0100" => estado<=Q5; when "1000" => estado<=Q10; when others => estado<=Q0; end case; when Q1 => case entrada_aux is when "0000" => estado<=Q1; when "0001" => estado<=Q2; when "0010" => estado<=Q3; when "0100" => estado<=Q6; when "1000" => estado<=Q11; when others => estado<=Q0; end case; when Q2 => case entrada_aux is when "0000" => estado<=Q2; when "0001" => estado<=Q3; when "0010" => estado<=Q4; when "0101" => estado<=Q7; when "1010" => estado<=Q12; when others => estado<=Q0; end case; when Q3 => case entrada_aux is when "0000" => estado<=Q3; when "0001" => estado<=Q4; when "0010" => estado<=Q5; when "0101" => estado<=Q8; when "1010" => estado<=Q13; when others => estado<=Q0; end case; when Q4 => case entrada_aux is when "0000" => estado<=Q4; when "0001" => estado<=Q5; when "0010" => estado<=Q6; when "0100" => estado<=Q9; when "1000" => estado<=Q14; when others => estado<=Q0; end case; when Q5 => case entrada_aux is when "0000" => estado<=Q5; when "0001" => estado<=Q6; when "0010" => estado<=Q7; when "0100" => estado<=Q10; when "1000" => estado<=Q15; when others => estado<=Q0; end case; when Q6 => case entrada_aux is when "0000" => estado<=Q6; when "0001" => estado<=Q7; when "0010" => estado<=Q8; when "0100" => estado<=Q11; when "1000" => estado<=Q16; when others => estado<=Q0; end case; when Q7 => case entrada_aux is when "0000" => estado<=Q7; when "0001" => estado<=Q8; when "0010" => estado<=Q9; when "0100" => estado<=Q12; when "1000" => estado<=Q17; when others => estado<=Q0; end case; when Q8 => case entrada_aux is when "0000" => estado<=Q8; when "0001" => estado<=Q9; when "0010" => estado<=Q10; when "0100" => estado<=Q13; when "1000" => estado<=Q18; when others => estado<=Q0; end case; when Q9 => case entrada_aux is when "0000" => estado<=Q0; when "0001" => estado<=Q1; when "0010" => estado<=Q2; when "0100" => estado<=Q5; when "1000" => estado<=Q10; when others => estado<=Q0; end case; when Q10 => case entrada_aux is when "0000" => estado<=Q0; when "0001" => estado<=Q1; when "0010" => estado<=Q2; when "0100" => estado<=Q5; when "1000" => estado<=Q10; when others => estado<=Q0; end case; when Q11 => case entrada_aux is when "0000" => estado<=Q0; when "0001" => estado<=Q1; when "0010" => estado<=Q2; when "0100" => estado<=Q5; when "1000" => estado<=Q10; when others => estado<=Q0; end case; when Q12 => case entrada_aux is when "0000" => estado<=Q0; when "0001" => estado<=Q1; when "0010" => estado<=Q2; when "0100" => estado<=Q5; when "1000" => estado<=Q10; when others => estado<=Q0; end case; when Q13 => case entrada_aux is when "0000" => estado<=Q0; when "0001" => estado<=Q1; when "0010" => estado<=Q2; when "0100" => estado<=Q5; when "1000" => estado<=Q10; when others => estado<=Q0; end case; when Q14 => case entrada_aux is when "0000" => estado<=Q0; when "0001" => estado<=Q1; when "0010" => estado<=Q2; when "0100" => estado<=Q5; when "1000" => estado<=Q10; when others => estado<=Q0; end case; when Q15 => case entrada_aux is when "0000" => estado<=Q0; when "0001" => estado<=Q1; when "0010" => estado<=Q2; when "0100" => estado<=Q5; when "1000" => estado<=Q10; when others => estado<=Q0; end case; when Q16 => case entrada_aux is when "0000" => estado<=Q0; when "0001" => estado<=Q1; when "0010" => estado<=Q2; when "0100" => estado<=Q5; when "1000" => estado<=Q10; when others => estado<=Q0; end case; when Q17 => case entrada_aux is when "0000" => estado<=Q0; when "0001" => estado<=Q1; when "0010" => estado<=Q2; when "0100" => estado<=Q5; when "1000" => estado<=Q10; when others => estado<=Q0; end case; when Q18 => case entrada_aux is when "0000" => estado<=Q0; when "0001" => estado<=Q1; when "0010" => estado<=Q2; when "0100" => estado<=Q5; when "1000" => estado<=Q10; when others => estado<=Q0; end case; when others => estado<=Q0; end case; end if; end process; process(estado) begin case estado is when Q0 => Sie1<="0000"; Sie2<="0000"; Sie3<="0000"; Sie4<="0000"; when Q1 => Sie1<="0000"; Sie2<="0001"; Sie3<="0000"; Sie4<="0000"; when Q2 => Sie1<="0000"; Sie2<="0010"; Sie3<="0000"; Sie4<="0000"; when Q3 => Sie1<="0000"; Sie2<="0011"; Sie3<="0000"; Sie4<="0000"; when Q4 => Sie1<="0000"; Sie2<="0100"; Sie3<="0000"; Sie4<="0000"; when Q5 => Sie1<="0000"; Sie2<="0101"; Sie3<="0000"; Sie4<="0000"; when Q6 => Sie1<="0000"; Sie2<="0110"; Sie3<="0000"; Sie4<="0000"; when Q7 => Sie1<="0000"; Sie2<="0111"; Sie3<="0000"; Sie4<="0000"; when Q8 => Sie1<="0000"; Sie2<="1000"; Sie3<="0000"; Sie4<="0000"; when Q9 => Sie1<="0000"; Sie2<="1001"; Sie3<="1111"; Sie4<="0000"; when Q10 => Sie1<="0001"; Sie2<="0000"; Sie3<="1111"; Sie4<="0001"; when Q11 => Sie1<="0001"; Sie2<="0001"; Sie3<="1111"; Sie4<="0010"; when Q12 => Sie1<="0001" ; Sie2<="0010"; Sie3<="1111"; Sie4<="0011"; when Q13 => Sie1<="0001" ; Sie2<="0011"; Sie3<="1111"; Sie4<="0100"; when Q14 => Sie1<="0001"; Sie2<="0100"; Sie3<="1111"; Sie4<="0101"; when Q15 => Sie1<="0001"; Sie2<="0101"; Sie3<="1111"; Sie4<="0110"; when Q16 => Sie1<="0001"; Sie2<="0110"; Sie3<="0001"; Sie4<="0111"; when Q17 => Sie1<="0001"; Sie2<="0111"; Sie3<="1111"; Sie4<="1000"; when Q18 => Sie1<="0001"; Sie2<="1000"; Sie3<="1111"; Sie4<="1001"; end case; end process; Sie1_i <= Sie1; -----Error here Sie1_i1 <= Sie2; -----Error here Sie1_i2 <= Sie3; -----Error here Sie1_i3 <= Sie4; -----Error here display_1: seg7 port map(Sie1_i, Sie11); display_2: seg7 port map(Sie1_i1,Sie21); display_3: seg7 port map(Sie1_i2,Sie31); display_4: seg7 port map(Sie1_i3,Sie41); end behavioral;
i cant find , or understand whats wrong
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