engr_joni_ee
Advanced Member level 3
VHDL compilation error "Identifier "unsigned" is not directly visible"
Hi,
I get an error (Identifier "unsigned" is not directly visible) while converting std_logic_vector to integer.
The signal and variable definition.
The libraries
Conversion
Hi,
I get an error (Identifier "unsigned" is not directly visible) while converting std_logic_vector to integer.
The signal and variable definition.
Code:
signal s_temp : std_logic_vector (7 downto 0);
variable i_temp : integer;
The libraries
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
Conversion
Code:
i_temp := to_integer(unsigned(s_temp));