VHDL coding -architecture phase

[Abisheak]

ARCHITECTURE netlist OF mux IS
COMPONENT andgate
PORT(a, b, c : IN bit; c : OUT BIT);
END COMPONENT;
COMPONENT inverter
PORT(in1 : IN BIT; x : OUT BIT);
END COMPONENT;
COMPONENT orgate
PORT(a, b, c, d : IN bit; x : OUT BIT);
END COMPONENT;
SIGNAL s0_inv, s1_inv, x1, x2, x3, x4 : BIT;
BEGIN
U1 : inverter(s0, s0_inv);
U2 : inverter(s1, s1_inv);
U3 : andgate(a, s0_inv, s1_inv, x1);
U4 : andgate(b, s0, s1_inv, x2);
U5 : andgate(c, s0_inv, s1, x3);
U6 : andgate(d, s0, s1, x4);
U7 : orgate(x2 => b, x1 => a, x4 => d, x3 => c, x => x);
END netlist;

I was starting to real VHDL and found this code.i realised the different components of mux but was unable to distinguish the parameters or generics passed.could some please help me ?Especially the code after BEGIN statement.

thank you

 

[FvM]

Try to sketch the circuit on paper. There are no generics or parameters involves, just actual port signals.

The component definition says what are the in and output signals, just trace the signal flow from top level inputs to outputs.

Unfortunately, there are several typos in the code, please refer to the original exercise problem. Output signal is apparently x not c (can't be the same name as input signal), and there's a signal d, I guess another input.

 

[Abisheak]

Tried figuring out with the circuit diagram. thank you mate. and i guess the AND gate should be changed to
COMPONENT andgate
PORT(a,b,c,d :IN bit ; x :OUT bit);
or should i leave out the ENABLE part of the mux connection?

or Does a,b,c,d refer to enable latch of the AND gate?

 

[FvM]

I still don't understand where you "found this code" which has serious errors.

The top entity should look like this:

PORT(a,b,c,d,s0,s1 :IN bit ; x :OUT bit);

In addition, the orgate port mapping has formal and actual names flipped. It's basically good to used named association, but you need to understand how it works.

 

[Abisheak]

I found this code in Doughlas perry's book on VHDL.If possible could u please suggest me some good VHDL book?

 

[FvM]

I didn't learn VHDL from a book. In my daily work I'm sometimes reviewing IEEE 1076.

From the books I have seen, I like Enoch O. Hwang, Digital Logic and Microprocessor Design With VHDL, but I'm sure there are many other good ones.

 

[Abisheak]

thanks dude.That is really helpful