sushma67
Junior Member level 1
library ieee;
use ieee.std_logic_1164.all;
entity shf is
port(I:in std_logic_vector(2 downto 0);Yut std_logic_vector(7 downto 0));
end shf;
architecture behaviour of shf is
begin
Y<=2^I;
end behaviour;
use ieee.std_logic_1164.all;
entity shf is
port(I:in std_logic_vector(2 downto 0);Yut std_logic_vector(7 downto 0));
end shf;
architecture behaviour of shf is
begin
Y<=2^I;
end behaviour;