VHDL Code for a pushbutton to produce an enable signal for a time delay generator

[kemalkemal]

hi all
i’m trying to realize a very small Project, for further and more complex projects . I wrote a synthesizable code to accomplish this – when i hit a pushbutton fpga should light a led and start a timer at the same time. After a predetermined time delay led is goint to off and timer will reset and wait for a new pushbutton command. (i have a terasic D0 board with cyclone iii).
For this i have 2 design files. One for time delay generator , with a generic variable named “delay” which is used for to produce time delay with a 50 Mhz clock . And the other design file is my top level entity which captures the hit to the pushbutton and send it as the enable signal for counter of time delay generator.
i get lots of error messages until i reach to this final code but i couldn’t get over the last error whic is Error (10822): HDL error at buton.vhd(23): couldn't implement registers for assignments on this clock edge.
somewhere in the forum said that it is impossible to use synchronous and asynchronous signal at the same time at the same device. I feel this is my fault but how can i fix it?

library ieee;
use ieee.std_logic_1164.all;
entity buton is 
port (clk,buton : in std_logic; 
led_delay_out std_logic);
end buton;

architecture behav of buton is
signal deljenen : std_logic;
signal deljenout: std_logic;
begin
inst_5s: entity work.delay_jen generic map (delay => 250000000) port map (clk,deljenen,deljenout);
led_delay<=deljenout;
process (buton)
begin
if falling_edge (buton) then 
deljenen <='1'; else
deljenen <='0';
end if;
end process;
end behav;

library ieee;
use ieee.std_logic_1164.all;
entity delay_jen is 
generic (delay : integer);
port( clk : in std_logic;
en : in std_logic;
flag: out std_logic);
end delay_jen;

architecture behv of delay_jen is
begin
process(clk)
variable count:integer:=0;
begin
if (en) then 
flag<='1'; count:=count+1;
if (count=delay) then count:=0; flag<='0'; end if;
end if;
end process;
end behv;

 

[ads-ee]

Your code has way too many problems, so I'm not going to go through and describe everything that is wrong. Your error line 23 doesn't exist in the code. Take a look at your post and count the number of lines :roll:

Instead I suggest you look at the examples of synthesizable code here. Then rewrite your code so they follow those templates.

Also you can't just use the falling edge of the button. Read about debouncing and use circuits like this to clean up the switch chatter and get a clean transition.

I also recommend as a new VHDL user that you not use variables. I only use them in very specific cases to make code more readable, and I never use them to model flip-flops (that's like gambling on the synthesis tool recognizing you wanted a flip-flop but didn't use <= as the assignment). After you really know the language and understand how variables work, then you might consider using them occasionally to improve code clarity.

 

[kemalkemal]

thanks ads-ee i will adhere to your advices.