abhineet22
Advanced Member level 4
Hi i have written one code..is it correct ? if yes then in wave form a and b will synchronizes to clk.because this is sequential modeling ..and waht will be the hardware generated by this code ??
entity g is
port(clk:in std_logic;
a,b ut std_logic);
end g;
architecture behav of g is
begin
process(clk)
begin
if (clk'event and clk ='1')then
a<='1';
b<='1';
else;
a<='0';
b<='0';
end if;
end process;
end behav;
entity g is
port(clk:in std_logic;
a,b ut std_logic);
end g;
architecture behav of g is
begin
process(clk)
begin
if (clk'event and clk ='1')then
a<='1';
b<='1';
else;
a<='0';
b<='0';
end if;
end process;
end behav;