superdave14
Newbie level 3
Hello guys/gals first post.
In a grad class, advanced digital logic and the instructor is learning with the students so thus far its been interesting. Needless to say a lot of self teaching. Anyways we are trying to build a 8 bit counter to count up to 99 then reset to send out to the 7 seg's and i am having issues with the code. I can get the lower 4 bits to count and reset to 0 after it reaches 8 with a 3.5 nanosecond propagation delay on the 10. The issue is when i try to increment the high nibble on the reset of the lower nibble it goes high for 10 nano but then resets back to zero and i have no idea why. Can someone help me with the code? Again im a complete noob and some of the code i figured out for myself through just trying stuff. Thanks
Guess it would help to note im using Quartus II version 9.1 SP2
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(7 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "00000000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
-- to split up the 8 bit bus use your bus name + the bus length such as
--tmp(3 downto 0) is the lower half of the 8 bits. This is how you islate the bus in
--in VHDL code. Figured it out all by myself.
if (tmp(3 downto 0) = "1001") then
tmp(3 downto 0) <= "0000";
tmp(7 downto 4) <= + "0001";
end if;
end process;
Q <= tmp;
end archi;
In a grad class, advanced digital logic and the instructor is learning with the students so thus far its been interesting. Needless to say a lot of self teaching. Anyways we are trying to build a 8 bit counter to count up to 99 then reset to send out to the 7 seg's and i am having issues with the code. I can get the lower 4 bits to count and reset to 0 after it reaches 8 with a 3.5 nanosecond propagation delay on the 10. The issue is when i try to increment the high nibble on the reset of the lower nibble it goes high for 10 nano but then resets back to zero and i have no idea why. Can someone help me with the code? Again im a complete noob and some of the code i figured out for myself through just trying stuff. Thanks
Guess it would help to note im using Quartus II version 9.1 SP2
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(7 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "00000000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
-- to split up the 8 bit bus use your bus name + the bus length such as
--tmp(3 downto 0) is the lower half of the 8 bits. This is how you islate the bus in
--in VHDL code. Figured it out all by myself.
if (tmp(3 downto 0) = "1001") then
tmp(3 downto 0) <= "0000";
tmp(7 downto 4) <= + "0001";
end if;
end process;
Q <= tmp;
end archi;
Last edited: