VGA display on a bigger monitor

[asong]

Hi all.

I am currently working on a VGA controller on Spartan 3E.

I found some textbook with example code on it. It is very basic, simply pixel counters and stuff to create hsync, vsync and the rgb just one set value.

It all synthesizes and I could generate a bit file and program the FPGA.

However, when I plug the vga cable in and try to get a blank white screen, the monitor displayed frequency out of range.

The example code was designed to display 640x480 with total number of pixels (including left/top, right/top and retrace pixels) of 800x525. and it was designed to be 60Hz, which all came together to be 25MHz, half the frequency of the clock on S3E.

The monitor was 15'' LCD, I tried with a 13'' inch CRT but nothing was displayed. I think it's the frequency problem again.

Do I need to find a tiny monitor or do I need to do something with the code to display colours on a screen bigger than 640x480?

Thank you very much

 

[keith1200rs]

Have you checked the frame and line rate you are producing with an oscilloscope?

Keith

 

[asong]

sorry I am new to FPGA, how should I check that ?

Added after 14 minutes:

With the code I am looking at right now. At every posedge of the 25MHz clock, the horizontal count increments by 1 until it reaches 799. Vertical count also increments by 1 until it reaches 524.

Shouldn't Vertical Count only increment when horizontal count has reaches 799?

 

[keith1200rs]

I assume you have a simulator to look at what your code does - that would be the first place to check. Otherwise, actually put an oscilloscope on the signals and check that the signals look correct.

But yes, you should only increment your line counter (vertical) when you have completed a line (horizontal).

Keith.

 

[kib]

vertical counter logic is wrong

check this vhdl code for vga sync generation (example code from rapid prototyping of digital systems)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY VGA_SYNC IS
PORT( clock_25MHz, red, green, blue : IN STD_LOGIC;
red_out, green_out, blue_out : OUT STD_LOGIC;
horiz_sync_out, vert_sync_out : OUT STD_LOGIC;
pixel_row, pixel_column : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 ));
END VGA_SYNC;
ARCHITECTURE a OF VGA_SYNC IS
SIGNAL horiz_sync, vert_sync : STD_LOGIC;
SIGNAL video_on, video_on_v, video_on_h : STD_LOGIC;
SIGNAL h_count, v_count : STD_LOGIC_VECTOR( 9 DOWNTO 0 );
BEGIN
-- video_on is High only when RGB data is displayed
video_on <= video_on_H AND video_on_V;
PROCESS
BEGIN
WAIT UNTIL( clock_25MHz'EVENT ) AND ( clock_25MHz = '1' );
--Generate Horizontal and Vertical Timing Signals for Video Signal
-- H_count counts pixels (640 + extra time for sync signals)
--
-- Horiz_sync -------------------------------------------________--------
-- H_count 0 640 659 755 799
--
IF ( h_count = 799 ) THEN
h_count <= "0000000000";
ELSE
h_count <= h_count + 1;
END IF;
--Generate Horizontal Sync Signal using H_count
IF ( h_count <= 755 ) AND (h_count => 659 ) THEN
horiz_sync <= '0';
ELSE
horiz_sync <= '1';
END IF;
--V_count counts rows of pixels (480 + extra time for sync signals)
--
-- Vert_sync ----------------------------------------_______------------
-- V_count 0 480 493-494 524
--
IF ( v_count >= 524 ) AND ( h_count => 699 ) THEN
v_count <= "0000000000";
ELSIF ( h_count = 699 ) THEN
v_count <= v_count + 1;
END IF;
-- Generate Vertical Sync Signal using V_count
IF ( v_count <= 494 ) AND ( v_count = >493 ) THEN
vert_sync <= '0';
ELSE
vert_sync <= '1';
END IF;
-- Generate Video on Screen Signals for Pixel Data
IF ( h_count <= 639 ) THEN
video_on_h <= '1';
pixel_column <= h_count;
ELSE
video_on_h <= '0';
END IF;
IF ( v_count <= 479 ) THEN
video_on_v <= '1';
pixel_row <= v_count;
ELSE
video_on_v <= '0';
END IF;
-- Put all video signals through DFFs to eliminate
-- any delays that can cause a blurry image
-- Turn off RGB outputs when outside video display area
red_out <= red AND video_on;
green_out <= green AND video_on;
blue_out <= blue AND video_on;
horiz_sync_out <= horiz_sync;
vert_sync_out <= vert_sync;
END PROCESS;
END a;

 

[mo.khairy.mo]

hi asong
i designed a vga controller on spartan 3e and tested it here is the code
please feel free to ask me about any confusing point

 

[umer_366]

ok if i do it on microblaze processor ll i be requiring the code for that???
if then in which language???

 

[kvingle]

i think your timing of hsync and vsync are not appropriate refer to these docs


http://www.epanorama.net/documents/pc/vga_timing.html
**broken link removed**


see if your output waveform matches to standards.
you will have to divide your 25 mhz clk properly.

 

[ablam]

Hai

Can u tel me how to display the image on monitor through VGA.Do u have any sample code for the same?
I need it for my academic project.plz help
simple example codis required in VHDL/verilog.Thanks in advance.it wil be a great help