Verilog, VHDL or mixed? What is your choice?

[jimjim2k]

mixed verilog vhdl

Hi



This is the result of a poll from Deepchip with 818 usesrs:
h**p://www.deepchip.com/items/dvcon07-02.html



A CLEARER PICTURE -- With 818 responses, this time around I was able to snag
a crisper view of the Verilog vs. VHDL world. Here's the older data:

2005 - "Does your project do mixed Verilog/VHDL simulations?"

Verilog only : ############################## 59%
mixed : ################### 38%
VHDL only : # 3%

Now here's the 2007 data with the break out of that vague "mixed" term:

2007 - "Does your project do mixed Verilog/VHDL simulations?"

Verilog only : ############################ 55.3%
mostly Verilog : ######### 18.0%
both equally : ### 6.5%
mostly VHDL : ######## 16.4%
VHDL only : ## 4.0%



Now:
What about EDABOARD users?
Select your choice please:

 

[khamitkar.ravikant]

verilog vhdl mixed

thanks alot for making us aware of such great poll

 

[jimjim2k]

mixed vhdl verilog

thanks alot for making us aware of such great poll

My hope is to have more than 818 of deepchip report poller.


tnx

 

[boardlanguage]

teaching mixed verilog/vhdl courses

This poll is for FPGA synthesis only, correct?

I'd like to see two extra choices:

1) Systemverilog
2) Altera HDL (AHDL)

And for the ancient engineers:
3) ABEL

Personally, I believe in Systemverilog ... unfortunately Xilinx ISE doesn't have it. (Altera Quartus-II supports SYstemverilog language quite well, so far.)

 

[jimjim2k]

mixed verilog with vhdl

This poll is for FPGA synthesis only, correct?

I'd like to see two extra choices:

1) Systemverilog

I think you must compare systemverilog with systemc. You are welcomed to do such poll.
In this case the following items are good to be compared

SystemVerilog
SystemC
Handel-C
SpecC

2) @ltera HDL (AHDL)

And for the ancient engineers:
3) ABEL

The main reason I did not add more items is to re-evaluate the results if deep-chip poll in 2008.
As you see from 2005 to 2007 the usage patterns changed slightly.
I want to learn the usage pattern of EDABOARD users in 2008.

Personally, I believe in Systemverilog ... unfortunately Xilinx ISE doesn't have it. (@ltera qu(at)rtus-II supports SYstemverilog language quite well, so far.)

As you mentioned in you post @
h**p://
Xilinx claims to begin Systemverilog synthesis in 2008



tnx

 

[THUNDERRr]

deepchip edaboard

verilog because it will help in understanding systtenverilog which has alot of advantages over vhdl