coolkwc
Newbie level 3
Verilog problem
module shiftregister(parallelin,load,w,clock,Q);
parameter n = 32;
input [n-1:0] parallelin;
input load,w,clock;
output reg [n-1:0] Q;
integer k;
always@(posedge clock)
if(L)
Q<=parallelin;
else
begin
for (k=0;k<n-1;k=k+1)
Q[k]<=Q[k+1];
Q[n-1]<=w;
end
endmodule
refer to the code above, i'm try to build the shift register which could parallel input or serial input...the code above consist of 32 flip-flop unit which everyone got 1 bit input and output...
My problem is now i wanna have 17bit for input and output on each flip-flop unit, so what parameter i should add in the code above? Hope you guys can help me, thanks...
module shiftregister(parallelin,load,w,clock,Q);
parameter n = 32;
input [n-1:0] parallelin;
input load,w,clock;
output reg [n-1:0] Q;
integer k;
always@(posedge clock)
if(L)
Q<=parallelin;
else
begin
for (k=0;k<n-1;k=k+1)
Q[k]<=Q[k+1];
Q[n-1]<=w;
end
endmodule
refer to the code above, i'm try to build the shift register which could parallel input or serial input...the code above consist of 32 flip-flop unit which everyone got 1 bit input and output...
My problem is now i wanna have 17bit for input and output on each flip-flop unit, so what parameter i should add in the code above? Hope you guys can help me, thanks...