vickyuet
Member level 2
Dear all,
As lots of books talk about inferring latches in hardware, when we miss few statements during coding like
1- not including else with if
2- not including default case with case statements....
but upon reading XST user manual examples I observed above are missings they not considered both of the above .....code snippet is below for reference.
else missing in first always and default case missing in second...:shock:
// though default case here is not as necessary bcz all cases are covered .....:!:
As lots of books talk about inferring latches in hardware, when we miss few statements during coding like
1- not including else with if
2- not including default case with case statements....
but upon reading XST user manual examples I observed above are missings they not considered both of the above .....code snippet is below for reference.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 // // ROMs Using Block RAM Resources. // Verilog code for a ROM with registered address // module v_rams_21c (clk, en, addr, data); input clk; input en; input [2:0] addr; output reg [19:0] data; reg [2:0] raddr; always @(posedge clk) begin if (en) raddr <= addr; end //Table look up always @(raddr) begin case(raddr) 3’b000: data <= 20’h0200A; 3’b001: data <= 20’h00301; 3’b010: data <= 20’h0200A; 3’b011: data <= 20’h00301; 3’b100: data <= 20’h0200A; 3’b101: data <= 20’h00301; 3’b110: data <= 20’h0200A; 3’b111: data <= 20’h00301; endcase end endmodule
else missing in first always and default case missing in second...:shock:
// though default case here is not as necessary bcz all cases are covered .....:!:
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