sharanyakhamithkar
Newbie level 4
Hi guys,
I was trying to write a RTL code for Gray to Binary conversion for N number of bits.
For this code, i am getting output of first two MSB bits, other two bits are coming as dont cares(X's).
Please let me know what went wrong?
I was trying to write a RTL code for Gray to Binary conversion for N number of bits.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module gray2binary(gr,bi); parameter N=4; input [N-1:0]gr; output reg [N-1:0]bi; integer i=N-2; always @(*) begin bi[N-1]=gr[N-1]; for (i=N-2;i==0;i=i-1) $display("Entering for loop"); bi[i]=gr[i]^bi[i+1]; end endmodule
For this code, i am getting output of first two MSB bits, other two bits are coming as dont cares(X's).
Please let me know what went wrong?