djc
Advanced Member level 1
Hello all,
I have just started learning verilog. Now trying to write APB protocol for master. Flow may not be correct so please consider that. However i am getting some error which i am unable to understand. Here is the design and testbench code.
Design Module
Testbench Module
And these are the errors
I am using ModelSim student vrsion. Can you please guide.
I have just started learning verilog. Now trying to write APB protocol for master. Flow may not be correct so please consider that. However i am getting some error which i am unable to understand. Here is the design and testbench code.
Design Module
Code:
module apb_master (pclk,prst,paddr,pwdata,prdata,pwrite,pread,psel,penable,pready);
parameter S_IDLE = 3'b000;
parameter S_SETUP = 3'b001;
parameter S_ACCESS = 3'b010;
input pclk;
input prst;
output reg [3:0] paddr;
output reg [7:0] pwdata;
input [7:0] prdata;
output reg pwrite;
output reg psel;
output penable;
output reg pread;
input pready;
//input wire pslverr;
reg [2:0] state, next_state;
reg Tr;
reg [7:0] yahoo;
reg [3:0] addr_bus;
reg [7:0] data_bus;
initial begin
if(prst)begin
paddr = 0;
pwdata = 0;
pwrite = 0;
psel = 0;
pready = 0;
//pslverr = 0;
end
end
always@(posedge pclk) begin
if(penable)begin
if(pready)begin
if(pwrite)begin
addr_bus = paddr;
data_bus = pwdata;
end
if(pread) begin
prdata = pwdata;
end
end
end
end
always @(next_state) begin
state = next_state;
end
always @(posedge pclk) begin
case(state)
S_IDLE:begin
psel = 0;
penable=0;
if (Tr == 1) begin
next_state = S_SETUP;
end
end
S_SETUP:begin
psel = 1;
penable = 0;
next_state = S_ACCESS;
end
S_ACCESS:begin
psel = 1;
penable = 1;
if (pready == 0) begin
next_state = S_ACCESS;
end
if((pready == 1) && (Tr == 1)) begin
next_state = S_SETUP;
end
end
endcase
end
endmodule
Testbench Module
Code:
`include"my_apb.v"
module tb;
reg pclk;
reg prst;
wire [3:0] paddr;
wire [7:0] pwdata;
reg [7:0] prdata;
reg pwrite;
wire psel;
wire penable;
wire pread;
reg pready;
//reg [2:0] state, next_state;
integer i;
//reg [3:0] addr_bus;
//reg [7:0] data_bus;
apb_master dut(.pclk(pclk),.prst(prst),.paddr(paddr),.pwdata(pwdata),.prdata(prdata),.pwrite(pwrite),.pread(pread),.psel(psel),.penable(penable),.pready(pready));
initial begin
//TB#1
pclk = 0;
forever #5 pclk = ~pclk; //#5 : 5ns
end
initial begin
prst = 1;
#1;
penable = 0;
prdata = 0;
pready = 0;
prst = 0;
#5;
penable = 1;
wait(pready == 1);
pwrite = 1;
for(i=0;i<10;i=i+1)begin
@(posedge pclk);
paddr = $random;
pwdata = $random;
end
@(posedge pclk);
pwrite = 0;
paddr = 0;
pwdata = 0;
#5;
pread = 1;
pwdata = $random;
#5;
pread = 1;
pwdata = 0;
end
endmodule
And these are the errors
Code:
ModelSim>vsim -novopt tb
# vsim
# Start time: 23:25:22 on Jan 01,2021
# Loading work.tb
# Loading work.apb_master
# ** Error (suppressible): (vsim-3053) tb_my_apb.v(16): Illegal output or inout port connection for port 'paddr'.
# Time: 0 ns Iteration: 0 Instance: /tb/dut File: my_apb.v
# ** Error (suppressible): (vsim-3053) tb_my_apb.v(16): Illegal output or inout port connection for port 'pwdata'.
# Time: 0 ns Iteration: 0 Instance: /tb/dut File: my_apb.v
# ** Error (suppressible): (vsim-3053) tb_my_apb.v(16): Illegal output or inout port connection for port 'pwrite'.
# Time: 0 ns Iteration: 0 Instance: /tb/dut File: my_apb.v
# ** Error (suppressible): (vsim-3053) tb_my_apb.v(16): Illegal output or inout port connection for port 'penable'.
# Time: 0 ns Iteration: 0 Instance: /tb/dut File: my_apb.v
# Error loading design
I am using ModelSim student vrsion. Can you please guide.