Verilog code for APB master

[djc]

Hello all,
I have just started learning verilog. Now trying to write APB protocol for master. Flow may not be correct so please consider that. However i am getting some error which i am unable to understand. Here is the design and testbench code.
Design Module

module apb_master (pclk,prst,paddr,pwdata,prdata,pwrite,pread,psel,penable,pready);

parameter S_IDLE = 3'b000;
parameter S_SETUP = 3'b001;
parameter S_ACCESS = 3'b010;
input pclk;
input prst;
output reg  [3:0] paddr;
output reg  [7:0] pwdata;
input  [7:0] prdata;
output reg  pwrite;
output reg psel;
output penable;
output reg pread;
input  pready;
//input  wire pslverr;
reg [2:0] state, next_state;
reg Tr;
reg [7:0] yahoo;

reg [3:0] addr_bus;
reg [7:0] data_bus;

initial begin
if(prst)begin
    paddr = 0;
    pwdata = 0;
    pwrite = 0;
    psel = 0;
    pready = 0;
        //pslverr = 0;
end
end

always@(posedge pclk) begin
    if(penable)begin
        if(pready)begin
            if(pwrite)begin
            addr_bus = paddr;
            data_bus = pwdata;       
            end            
            if(pread) begin
            prdata = pwdata;
            end
        end
    end
end

always @(next_state) begin
    state = next_state;
end


always @(posedge pclk) begin
case(state)
    S_IDLE:begin
    psel = 0;
    penable=0;
        if (Tr == 1)  begin
            next_state = S_SETUP;
        end
    end

    S_SETUP:begin
    psel = 1;
    penable = 0;
    next_state = S_ACCESS;   
    end

    S_ACCESS:begin
    psel = 1;
    penable = 1;
        if (pready == 0)  begin
            next_state = S_ACCESS;   
        end
        if((pready == 1) && (Tr == 1)) begin
            next_state = S_SETUP;
        end       
    end
endcase

end
endmodule

Testbench Module

`include"my_apb.v"
module tb;
reg pclk;
reg prst;
wire [3:0] paddr;
wire [7:0] pwdata;
reg [7:0] prdata;
reg pwrite;
wire psel;
wire penable;
wire pread;
reg pready;
//reg [2:0] state, next_state;
integer i;
//reg [3:0] addr_bus;
//reg [7:0] data_bus;

apb_master dut(.pclk(pclk),.prst(prst),.paddr(paddr),.pwdata(pwdata),.prdata(prdata),.pwrite(pwrite),.pread(pread),.psel(psel),.penable(penable),.pready(pready));

initial begin
    //TB#1
    pclk = 0;
    forever #5 pclk = ~pclk;  //#5 : 5ns
end

initial begin
    prst = 1;
    #1;
    penable = 0;
    prdata = 0;
    pready = 0;
    prst = 0;
    #5;
    penable = 1;
    wait(pready == 1);
    pwrite = 1;
    for(i=0;i<10;i=i+1)begin
    @(posedge pclk);

    paddr = $random;
    pwdata = $random;   
    end
    @(posedge pclk);

    pwrite = 0;
    paddr = 0;
    pwdata = 0;
    #5;
    pread = 1;
    pwdata = $random;
    #5;
    pread = 1;
    pwdata = 0;
end
endmodule

And these are the errors

ModelSim>vsim -novopt tb
# vsim
# Start time: 23:25:22 on Jan 01,2021
# Loading work.tb
# Loading work.apb_master
# ** Error (suppressible): (vsim-3053) tb_my_apb.v(16): Illegal output or inout port connection for port 'paddr'.
#    Time: 0 ns  Iteration: 0  Instance: /tb/dut File: my_apb.v
# ** Error (suppressible): (vsim-3053) tb_my_apb.v(16): Illegal output or inout port connection for port 'pwdata'.
#    Time: 0 ns  Iteration: 0  Instance: /tb/dut File: my_apb.v
# ** Error (suppressible): (vsim-3053) tb_my_apb.v(16): Illegal output or inout port connection for port 'pwrite'.
#    Time: 0 ns  Iteration: 0  Instance: /tb/dut File: my_apb.v
# ** Error (suppressible): (vsim-3053) tb_my_apb.v(16): Illegal output or inout port connection for port 'penable'.
#    Time: 0 ns  Iteration: 0  Instance: /tb/dut File: my_apb.v
# Error loading design

I am using ModelSim student vrsion. Can you please guide.

 

[Stultus Verus]

Those ports are declared as output but you also assign values to them in the testbench. This is illegal.

 

[djc]

Thanks for the reply sir,
However how to assign values to output port then. It is APB master, it will select the slave, it means data has to be govern by master, so ports must be declared as output if i am not wrong. So if this is wrong can you please tell me the right way.

 

[Stultus Verus]

Thanks for the reply sir,
However how to assign values to output port then. It is APB master, it will select the slave, it means data has to be govern by master, so ports must be declared as output if i am not wrong. So if this is wrong can you please tell me the right way.

I cannot understand what you are trying to do from your code. What is register Tr? It is not driven at all. And you have this:

---

Code Verilog - [expand]
1
2
3
always @(next_state) begin
    state = next_state;
end

---

which is triggered every time next_state is changed instead of once a cycle.

APB is used for bridging low-bandwidth peripherals. The APB bridge works as a slave of another bus, e.g. AXI, then the master should be an AXI bus. If you are trying to implement the bridge here, you take AXI input and decode them, generating those output signals (paddr, ...), and implement slaves to receive them.

 

[djc]

Hello sir,
Thank you for clearing the concept of APB master and APB slave. I was thinking that APB slave can be interfaced to APB master. So any peripheral using APB protocol will act as a slave and will use APB slave protocol and this will ultimately get connected to a processor using APB master.
But i was wrong. Thank you once again.

 

[matrixofdynamism]

Just wondering, why do you need an APB master in this age? APB is a rather old interface by today's standards. New designs are not very likely to use it as there are better alternatives.

 

[ads-ee]

Just wondering, why do you need an APB master in this age? APB is a rather old interface by today's standards. New designs are not very likely to use it as there are better alternatives.

So what is the point of it being old? Being an old interface doesn't make it an less useful.

e.g. If you have an IP core for a SPI master that has an APB slave interface on it are you going to go buy or write a new IP core that has whatever brand spanking new Ferrari interface on it that has 1Tbps bandwidth?

Personally I would just slap that SPI master IP core that was used before and just write a bridge (or use the one that was previously written) to interface my AXI, AHB, Wishbone, etc bus to the APB.

 

[TrickyDicky]

Just wondering, why do you need an APB master in this age? APB is a rather old interface by today's standards. New designs are not very likely to use it as there are better alternatives.

Just because something is "old" doesnt automatically obsolete it. i2C is more than twice the age of APB and is still used on just about every chip made. Then what about RS232 and RS422? still pretty standard and 60 and 45 years old respectively.