ecasha
Junior Member level 2
Code:
module opr(clock,di,dread,adr,in1,sum1,cmct);
input clock;
input [0:5] di;
reg [3:0] pn1;
input [3:0] in1;
output [0:5] dread;
input [1:0] adr;
reg [3:0] k;
output [5:0]sum1;
reg [5:0]sum1;
output [3:0] cmct;
reg [3:0] cmct;
integer i,j;
reg [0:5] ram1[0:3];
reg en=1;
initial begin
for (i=0; i<=3; i=i+1)
begin
ram1[i] <= 2'b00; // memory initialization
end
end
assign dread = ram1[adr];
always @(posedge clock)
begin
if(en) begin //storing in memory
ram1[adr] <= di;
end
end
initial begin sum1=0; k=4'bzzzz; end
always @ (in1) begin
sum1=0;
for (i=0; i<=3; i=i+1)begin
for(j=0; j<6; j=j+1)begin // calculating number of 1's
sum1= sum1+ram1[i][j];
end
end
if (sum1 >=6'b000110) begin
pn1 = in1-4'b0001;
cmct= pn1;
k=pn1; end
else cmct=k; //storing counter value in an array
end
endmodule
I have written code for storing the results in memory and calculating the number of one's.in1 input is counter input. counter counts after every 4 clock pulses.For every counter input (i.e in1)number of one's in memory is calculated.if that sum is greater than 6 counter value is stored in an array. I have simulated code.There are no errors. But when i dump on vertex-5 FPGA kit,Correct values are not coming.Is there any problem in this code? how should I find it? Please Help me...(No sysnthesis errors)