beginner_EDA
Full Member level 4
Code Verilog - [expand] 1 2 3 4 5 6 7 8 always @(posedge clk) begin x<=1'b1; // First Assignment if (y) begin //some condition met x <= 1'b1; // Second Assignment end end
I would like to know in above code when also condition met which assignment will be executed although both assignments are same? First Assignment or Second Assignment?