goldeboy
Junior Member level 3
cadence ams
Hello,
I want to test a model of an op amp in Cadence written in Verilog-AMS. I have compiled the verilog-ams code successfully. I have also created the symbol. But I have found problem when I have tried to put the symbol in a schematic window and simulate a test bench circuit. I think there is a configuration : creating a config view etc..
Please, I need your help: Have you any example explaining how to simulate a test-bench circuit in cadence with a verilog-ams module?
Thank you very much.
Hello,
I want to test a model of an op amp in Cadence written in Verilog-AMS. I have compiled the verilog-ams code successfully. I have also created the symbol. But I have found problem when I have tried to put the symbol in a schematic window and simulate a test bench circuit. I think there is a configuration : creating a config view etc..
Please, I need your help: Have you any example explaining how to simulate a test-bench circuit in cadence with a verilog-ams module?
Thank you very much.