deep_sea
Advanced Member level 4
Hi all,
I have a non technical questions for guys who use Verilog-A or similar description language in their work. I can see that many fundamental blocks are already modelled in Cadence ahdl library. Why do some job ads require experience in HDL behavioural modelling?
I ask the question in another way. If I want to improve my chances in applying for such jobs who use behavioural modelling of analogue/RF building blocks, what models should I develop or master?
I have a non technical questions for guys who use Verilog-A or similar description language in their work. I can see that many fundamental blocks are already modelled in Cadence ahdl library. Why do some job ads require experience in HDL behavioural modelling?
I ask the question in another way. If I want to improve my chances in applying for such jobs who use behavioural modelling of analogue/RF building blocks, what models should I develop or master?
