Verilog-A simulation error in Virtuoso

[wandoo]

Hi,

I am trying to setup my Cadence Virtuoso (w/ MMSIM) environment and facing with this kind of error when using sth related to Verilog-A in the test schematic.

I found some people who had similar issues on google and Cadence support pages,
and tried what's suggested to solve it.

1. In ADE environment options, check "run with 64b" option and and add "-ac 0" user cmdline
-> no effect
2. check tool versions and machine environment
: IC6.1.8-64b.500.24
: MMSIM151.394
: I am on Windows 11 WSL with CentOS 7.9. (if it matters..)

-> guess everything is running on 64b, tools are new enough

3. export CDS_AHDLCMI_ENABLE=NO
-> no effect

4. and I this log in ahdlcmi.out

Any ideas will help!
Thanks in advance.

 

[Dominik Przyborowski]

Have you file /lib/ld-linux.so.2?
MMSIM15 is rather prehistoric so it might looking for library which has different name now.

 

[wandoo]

Have you file /lib/ld-linux.so.2?
MMSIM15 is rather prehistoric so it might looking for library which has different name now.

It works right after installing ld-linux.so.2. Took me 3 days struggling and you fixed in 1min. Thank you so much!