Verilog-A and Verilog-AMS

[Ansunamu]

what's different between Verilog-A and Verilog-AMS ? Which one is better ?

 

[flyinspace]

I think Verilog-A is the verilog language which can discribe the analog circuit. However, V-AMS can discribe the mixed signal circuit. So V-AMS can do more thing than V-A.

 

[borodenkov]

Verilog-A is analog only spec. Verilog-AMS allows both analog and digital. It includes Verilog-A as a subset.

Look here for details:

http://www.eda.org/verilog-ams/htmlpages/overview.html

 

[Ansunamu]

Ok , i see

Which EDA tool vendor provide the best tool for Verilog-A or Verilog-AMS ?

 

[tlihu]

Ok , i see

Which EDA tool vendor provide the best tool for Verilog-A or Verilog-AMS ?

Cadence is the EDA vendor that leads the spec. Verilog-A/-AMS. So, what do you think?

 

[niko_zhang]

test

 

[hgby2209]

Which simulator can support verilog-a and verilog-ams?

 

[zhan]

Cadence LDV 5.1 can upport AMS

 

[hgby2209]

LDV 5.1 can upport AMS, LDV 5.0 can or can't?
Modelsim can or can't?

 

[flyinspace]

I think LDV5.0 also can support AMS.
However, modelsim can not.

 

[pci1000]

ldv is just a simlator or it is the whole flow series?

 

[uncle_urfi]

Tools have to be licensed separately.
for instance at our installation we have the licence for verilog-a, verilog-ams and vhdl but not vhdl-ams. We are running LDV5.0.

The tools that integrates them all is the Cadence AMS designer. For further informationl, goto cadence.com and there sign up for the real-video demonstrations (around 8 of them, total of 10 hours) will keep you busy over the weekend.

IC5 + Spectre also supports verilog-ams and verilog-a, others i haven't tried, but i am sure you can license tools separately. The obvious limitation comes when you need to switch between say "behavioral" and "schematic" or "extracted" view. To change views efficiently, it is nice to have the AMS Designer.

Happy exploring.

---
To answer the original question. verilog-a had disciplines. For instance "electrical", "thermal" etc. Two nets with different disciplines couldn't be connected without a proper interface block. Verilog-AMS has mixed signal extensions and now includes disciplines like "logic" that define the digital areas of your circuit. So it is a superset of verilog-a.

 

[mrhfw]

pls post the full standard of verilgo-ams
thanks

Richard

 

[uncle_urfi]

The full documents are in megabytes, you can download them from the IEEE Xplore website. (references below)
------------------------------------------
Verilog AMS manual can be downloaded here:

http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/2.1/AMS-LRM-2-1.pdf
-----------------------------------------------------------------
IEEE Std 1364-2001
Year: 2001
IEEE standard Verilog hardware description language

Page(s): 0_1- 856
[Abstract] [PDF Full-Text (3773 KB)]

-----------------------------------------------------------------
IEEE Std 1076.1-1999
Year: 1999
IEEE standard VHDL analog and mixed-signal extensions

Page(s):
[Abstract] [PDF Full-Text (928 KB)]


--------------------------------------------------------------------------------
IEEE Std 1076-2002 (Revision of IEEE Std 1076, 2002 Edn)

Year: 2002
1076 IEEE Standard VHDL Language Reference Manual

Page(s): 0_1-300
[Abstract] [PDF Full-Text (1910 KB)]
--------------------------------------------------------------------

 

[duncan94022]

uncle_urfi,

"Tools have to be licensed separately.
for instance at our installation we have the licence for verilog-a, verilog-ams and vhdl but not vhdl-ams."

verilog-a is included in both spectre and ams designer. ams designer includes verilog-a, verilog-ams, and vhdl-ams. You get them all with ams designer and they are not licensed seperately. Something is messed up with your installaton if you have verilog-ams and not vhdl-ams. At least that is true for IC 5.0.x.

 

[labodhibo]

uncle_urfi,
Spectre does not support verilogAMS, it supports only verilogA and
ahdl(spectreHdl).

 

[labodhibo]

And Duncan is right about amsDesigner.
It supports all the languages including behavioral level.
In vhdlAMS, there are some limitations when you use along with
verilogAMS.
Labo

 

[triwolf]

LRM already have version 2.2

 

[ship_baba]

how to simulate in model sim or in aldec

 

[Hunter_BJUT]

almost the same