[SOLVED] Verilog 2001 and Ports with widths based upon parameters?

[Gizmotoy]

I'm new to Verilog, but have a bunch of experience in VHDL. I'm trying to replicate something I accomplish with Generics in VHDL, but I'm having a bit of trouble.

I understand that you could define port widths in pre-2001 Verilog using something like:

module adder (a,b,c);
parameter WIDTH = 2; //defult value
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
output [WIDTH-1:0] c;​

However, can the same thing be accomplished using the new module syntax made possible in Verilog 2001? I prefer that syntax since it's more compact and keeps ports and types together, but I can't figure out how to make it work. I figured something like:

module adder (
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
output reg [WIDTH-1:0] c);
parameter WIDTH = 2; //defult value​

But of course it complains that WIDTH is undefined. If I move the parameter definition above the module definition it compiles, but crashes my simulator (Active-HDL).

Is there a way to use the new syntax with port widths based on parameters? I feel like I must be missing something obvious, but I just don't see it. Thanks!

 

[permute]

verilog introduces a new format for this.

module a #(
    parameter B = 1
  ) (
    output reg q;
    input      d;
    input      clk
  );

and then

  a #(
      .B(1)
   ) uut (
     .q  (Q),
     .d  (D),
     .clk(clk)
   );

which follows VHDL's generic/port conventions fairly close.

 

[Gizmotoy]

Thank you! That worked perfectly. I was hoping there was a way to do this with the newer syntax. Thanks again.