dpaul
Advanced Member level 5
I am still writing complex self-checking test-benches in VHDL-2008 to exercise my DUT. I would like to move to some Opensource Verification methodology.
Two of them I came across are OSVVM and UVVM. I would need suggestions as to which one would be better to stick to.
UVVM has been released after OSVVM and Bitvis summaries its advantages here:
http://bitvis.no/dev-tools/uvvm/
One thing that is bugging me is the Supported simulators for Bitvis UVVM - "Vivado: Awaiting proper VHDL 2008 support" (I am mostly using Vivado simu).
Anyone knows how-much of hindrance Vivado 2018.3 brings in for UVVM implementation (it is known that Vivado does not support all of VHDL2008)?
Two of them I came across are OSVVM and UVVM. I would need suggestions as to which one would be better to stick to.
UVVM has been released after OSVVM and Bitvis summaries its advantages here:
http://bitvis.no/dev-tools/uvvm/
One thing that is bugging me is the Supported simulators for Bitvis UVVM - "Vivado: Awaiting proper VHDL 2008 support" (I am mostly using Vivado simu).
Anyone knows how-much of hindrance Vivado 2018.3 brings in for UVVM implementation (it is known that Vivado does not support all of VHDL2008)?