Verification Architecture for Microcontrollers using VMM

[jeevs]

Hi All,

Most of the current environment present for verifying the micro controllers are directed ASM based one.Where the testing is done based on direct testcases features for each of the functionality.I would like to get rid of the ASM based environment using the system verilog & VMM.Use the available methods like constrained random based,I have to prove that the new features available is better off than the conventional directed testcases method used.

I need help in creating an verification architecture.As I have started the paper work here I need help as in the conventional method the ASM are converted to hex file which is preloaded into a memory from where the DUT takes on....IS there any work around or how this should be added in a CRT method.


Please give your valuable suggestions so that I can improve on my verification architecture.Are there any papers present on this please provide me what ever information that is available.

Regards,
Jeevs

 

[koggestone]

to get faster response , u may also post your VMM related requests
at the following VMM forum
http://www.vmmcentral.org/forums/viewforum.php?f=2

for OVM related stuff
**broken link removed**

for general Functional Verification related stuff
**broken link removed**

 

[skyfaye]

I have never believe CRT methodology is better than the Directed methodology. We just finished a project with 2 fpgas, the more complex fpga was done using the Directed methodology and the less complex fpga was verified using the CRT methodology. We were able to fully verified the more complex fpga in significantly less time AND with less engineer. I like to see someone prove that the CRT methodology, which can give you more coverage faster, means faster verification time.

Instead of loading the stimulus from a file into memory, which is not a very good way of doing that, you can write the BFM with generica APIs to drive the stimulus. For example,

// pseudocode of file my_driver.sv

class my_driver {
task write (bit [7:0] addr, bit [31:0] data) {
}

task read (bit [7:0] addr, ref bit [31:0] data) {
}
}

 

[Syswip]

Hi skyfaye,

Using VMM doesn't imply that you should use only random tests. You are free to use VMM to write direct tests.

Bests,
Tiksan

 

[Syswip]

Hi skyfaye,

Could you please describe in couple of words what do you mean by CRT and Direct test environment.

I found that different people are thinking different. As I understand there is no exact border which is separating Direct from CRT.

Waiting for your response,
Thanks,
Tiksan

 

[skyfaye]

A Directed testing methodology is a feature-driven approach to verification. Whereas a CRT testing methodology is a coverage-driven approach to verification.
For any major project, a verification test plan is require and often than not, it is done by listing all the features to be tested. With Directed testing, the test is crafted so that the directed stimulus will completely test the feature, without any doubt. Whereas with CRT, the test is usually constrain-random, but still random, which might mean you don't know for sure the random stimulus will completely test the feature. So what's typically done in this case is use an additional tool, functional coverage, to make sure.