variation in clock skew and latency numbers

[jaya sree]

Hai everyone

In my project , at cts stage , after clock routing , below are the cts reports

clock skew : 0.030 ns
clock latency : 0.354 ns

at route stage again clock is routed, after that whole design is routed.Then extraction is done by Star extraction tool by synopsys. Then clock reports with SI ANALYSIS ON is generated by primetime.

clock skew : 0.131 ns
clock latency : 0.421 ns

Is this difference in skew and latency numbers acceptable ? Is the difference due to si analysis ON ? or clock routing has changed. How to find out clock routing has changed ?


please help me.I am using ICC and encounter tool

thank you
jaya sree

---------- Post added at 07:34 ---------- Previous post was at 07:27 ----------

the commands used at Iccts are :

report_clock_timing -nosplit -type skew > rpts/IcCts/clock_timing_skew.rpt
report_clock_timing -nosplit -type latency > rpts/IcCts/clock_timing_latency.rpt

the commands used for Primetime are ( FuncTT , 0.85 v , typrc 110c )
set si_enable_analysis true
run_command -timer "clock summary" -command "report_clock_timing -nosplit -type summary" -output "clock_summary.rpt"
set si_enable_analysis false

 

[jeet_asic]

Use report_clock_tree command , it will tell you in detail about ur clock tree , then go for report_timing . After CTS , tool tries to optimize timing , so it adds buffers to achieve its goal. If your goals r being achieved , then "probably" skew n latency is acceptable , it all depends on level/goal which u have specified for your design.

 

[jayfcam]

jaya sree,

latency numbers can be accepted. Can you tell me if clock skew numbers are global skew or local skew? By any chance did you turned on use of useful skew to meet timing? if that is the case and your timing is good. no need to worry.

Jay

 

[pavanks]

There are many factors here which might cause the variations in skew and latency.

1. There would be a diff in delays calculated by estimated delay model after CTS and Routing which used parasitic extracted values.
2. The SI might also be the reason. Try minimizing the coupling cap. That might help.
3. If u use useful skew to fix the setup violations that might have added some buffers which would have increased ur skew and latency.

Pls check the clock period. If it is less than 5 percent then this would be acceptable. But need to analyze though.