aditya1579
Member level 2
HI,
Is there a variable in design compiler which I can set to tell it to use clock gating cells only from the rtl and not add its own ?
Request some details please, thanks.
Thanks,
Aditya
Is there a variable in design compiler which I can set to tell it to use clock gating cells only from the rtl and not add its own ?
Request some details please, thanks.
Thanks,
Aditya