hallovipin
Member level 1
Hi,
I am new to verilog. Whatever material I have across over a month , all suggest that we should always try to avoid using blocking assignment.
I know the literature says that we should use <= for sequential and = for combinational.
But can somebody make it clear how to write given code with the help of <=
module (a,b,c,d,step1,step2,final_value,clk);
input [7:0] a,b,c,d;
output reg step1, step2, final_value;
always @(posedge clk) begin
step1=a+b;
step2=step1+c-d;
final_value=final_value+step2;
end
end module
now problem is if we use <= in simulation I dont get proper values of final_value.
how to use <= at a place when calculated value of the above expression is fed back to the next expression; (as shown in code)
They say that <= prevents generation of race condition.
But what I found that if I carefully place = in the code it works better.
Why is it a SIN to use = in Verilog.
Please suggest can I use <= for above software.
I am new to verilog. Whatever material I have across over a month , all suggest that we should always try to avoid using blocking assignment.
I know the literature says that we should use <= for sequential and = for combinational.
But can somebody make it clear how to write given code with the help of <=
module (a,b,c,d,step1,step2,final_value,clk);
input [7:0] a,b,c,d;
output reg step1, step2, final_value;
always @(posedge clk) begin
step1=a+b;
step2=step1+c-d;
final_value=final_value+step2;
end
end module
now problem is if we use <= in simulation I dont get proper values of final_value.
how to use <= at a place when calculated value of the above expression is fed back to the next expression; (as shown in code)
They say that <= prevents generation of race condition.
But what I found that if I carefully place = in the code it works better.
Why is it a SIN to use = in Verilog.
Please suggest can I use <= for above software.