urgent: floating point division in vhdl

[ranbi]

I did a pipeline divider and when i needed the block i discovered that i need the result to be in floating point representation. I dnt have enough time to write a new floating point divider.

this is the code is it possible to just change convert the result into floating point

Entity Division Is
port(
Clock : in std_logic;
Reset : in std_logic;
Load : in std_logic;
Num : in std_logic_vector(31 downto 0);
Den : in std_logic_vector(31 downto 0);
Ready : out std_logic;
Quotient : out std_logic_vector(31 downto 0);
Rem : out std_logic_vector(31 downto 0)
);
end Division;

architecture Division_RTL of Division is


constant ALL_ZERO : std_Logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal ni : std_logic_vector(63 downto 0);
signal sub : std_logic_vector(63 downto 0);
signal n : std_logic_vector(63 downto 0);
signal i : std_logic_vector(63 downto 0);
signal d : std_logic_vector(63 downto 0);
signal d_int : std_logic_vector(31 downto 0);
signal counter : std_logic_vector(5 downto 0);
-- attribute syn_keep : boolean;
-- attribute syn_keep of d_int, N : signal is true;
signal ReadTempo : Std_Logic;

begin

Ready <= ReadTempo;

NI(63 downto 0) <= ALL_ZERO & Numerateur;
D(30 downto 0) <= "0000000000000000000000000000000";
D(62 downto 31) <= d_int;
D(63) <= '0';
Quotient <=n(31 downto 0);
Rem <=n(63 downto 32);

Process(Reset, ReadTempo, n ,d )
Begin
If Reset = '1' Then
sub <= (Others=>'0');
ElsIf ReadTempo = '0' Then
sub<= n - d;
Else
sub <= (Others=>'0');
End If;
End Process;

Process(clock, reset, ReadTempo)
begin
If Reset = '1' Then
n(63 downto 0) <= (Others=>'0');
D_Int(31 downto 0) <= (others=>'0');
ElsIf Rising_Edge(Clock) Then
If load='1' Then
n(63 downto 0) <= NI(63 downto 0);
D_int(31 downto 0) <= Den(31 downto 0);
Else
If ReadTempo ='0' Then
n(63 downto 0) <= I(63 downto 0);
End If;
End If;
End If;
End Process;




Would it be better to use a fixed point conversion to floating point at this point and if so can someone send me a code for that.

Thanks

 

[TrickyDicky]

there is no usable floating point in VHDL. You will have to use an IP core (xilinx and altera provide them for free).