urgent: correct format for bit_vector to std_logic_vector conversion

[ranbi]

i need to convert En to bit_vector to do the srl in vhdl and I need to reconvert back to std_vector_logic for the second operation plz can anyone help me out with the correct syntax:

my part code:

signal En: std_logic_vector (31 downto 0);

En<= En srl 8;

Thanks

 

[lucbra]

I would avoid using srl (shift functions) and write them explicit. No need to make a conversion then.

 

[TrickyDicky]

whats wrong with the good old:

en <= x"00" & en(31 downto 8);

 

[ranbi]

yeh i ended up doing that i forgot abt doing that before