Valerius
Newbie level 4
Hi,
I'm trying to debug my code which takes 4x4 keypad inputs and displays the corresponding key index to the seven segment 2 digit display. However I encountered with the following warning:
which points to the indicated areas in my code:
The reason that I have this event control is to create my own specific timing control on my FPGA board. Since it is not a simulation I had to do it via counter.
Thank you.
I'm trying to debug my code which takes 4x4 keypad inputs and displays the corresponding key index to the seven segment 2 digit display. However I encountered with the following warning:
Code:
ERROR:Xst:850 - "topModule.v" line 60: Unsupported Event Control Statement.
ERROR:Xst:850 - "topModule.v" line 63: Unsupported Event Control Statement.
which points to the indicated areas in my code:
Code:
module topModule(pROW, pCOL, CLK, AN, sevenSegment);
input CLK;
output [3:0] pROW; //Row to be written
input [3:0] pCOL; //Column to be read
output reg [3:0] AN; //Anode output
output reg [6:0] sevenSegment; //Seven Segment data to display
reg [3:0] currentValue; //Register that holds the last output value BUT it is 1 less !!!
wire [6:0] DigOUT1; //Both digit values
wire [6:0] DigOUT0;
wire [3:0] keyOUT;
wire EN1, EN0;
parameter One = 7'b1001111; //When the index value is bigger than nine, display
//the tenths decimal digit one with this parameter
keypadScanner keySch(pROW, pCOL, keyOUT, CLK);
sevenSegDecoder ssegDECDig1(One, DigOUT1, EN1);
sevenSegDecoder ssegDECDig0((keyOUT + 1), DigOOUT0, EN0); //Add 1 since we lost 1 in keySch
assign EN1 = 1'b1 ? keyOUT > 9 : 1'b0;
assign EN0 = 1'b1;
//2:1 Multiplexer which displays the digits about 800Hz
reg [15:0] count;
wire ticker;
always @(posedge CLK) count <= count + 1;
assign ticker = &count;
always begin
currentValue <= keyOUT;
if(currentValue > 9) begin
AN <= 4'b1110;
sevenSegment <= DigOUT0;
@(posedge ticker) //<------ POINTS TO HERE
AN <= 4'b1101;
sevenSegment <= DigOUT1;
@(posedge ticker); //<----- POINTS TO HERE
end
else begin
AN <= 4'b1110;
sevenSegment <= DigOUT0;
end
end
endmodule
The reason that I have this event control is to create my own specific timing control on my FPGA board. Since it is not a simulation I had to do it via counter.
Thank you.