FecP
Newbie level 6
Hello! I have tried to understand the set_input_delay and set_output_delay constraints, and I'm still confused. First off, here's what I think the set_input_delay command does :
The register associated with the physical input pins of the FPGA is clocked after the max TCO of the external device with which the device is interfaced.Say, that the external device has a TCOmax of 25 ns and the set_output_delay -max is set to 25ns as well.To me, it looks like this makes certain that the input register latches data at t >= 25 ns. Is it so? Just to be clear,this mechanism looks a little something like this(in my head) :
1) Let's say that at t = 0, we have a rising edge on the clock.(Device and FPGA have same clock).
2) The external device outputs data at 25ns (TCO max).
3) Let's assume further there are two registers.One is the Input Register(with its inputs connected to the pins), and the other is a simple register, connected in cascade/series with the input register.
Now, when I set the output_delay to 25 ns, I imagine that the Input Register and the other register get clocked differently.(Assuming a 37ns clock period)
To me, the input register gets its clock pulse at 25, 25 + 37 , 25 + 2*37 ,..........., 25 + n*37.
And the other register is clocked at 37, 37 + 37, 37 + 2*37,......,37 + n*37.
If it is truly so, then there would only be a (37 - 25)ns delay between the value getting latched into the input register and then going to the cascaded register?
Have I got it right? This has me really confused.Sorry for the long post!
The register associated with the physical input pins of the FPGA is clocked after the max TCO of the external device with which the device is interfaced.Say, that the external device has a TCOmax of 25 ns and the set_output_delay -max is set to 25ns as well.To me, it looks like this makes certain that the input register latches data at t >= 25 ns. Is it so? Just to be clear,this mechanism looks a little something like this(in my head) :
1) Let's say that at t = 0, we have a rising edge on the clock.(Device and FPGA have same clock).
2) The external device outputs data at 25ns (TCO max).
3) Let's assume further there are two registers.One is the Input Register(with its inputs connected to the pins), and the other is a simple register, connected in cascade/series with the input register.
Now, when I set the output_delay to 25 ns, I imagine that the Input Register and the other register get clocked differently.(Assuming a 37ns clock period)
To me, the input register gets its clock pulse at 25, 25 + 37 , 25 + 2*37 ,..........., 25 + n*37.
And the other register is clocked at 37, 37 + 37, 37 + 2*37,......,37 + n*37.
If it is truly so, then there would only be a (37 - 25)ns delay between the value getting latched into the input register and then going to the cascaded register?
Have I got it right? This has me really confused.Sorry for the long post!