bazook
Newbie level 5
Hi,
Ive designed something and have very big problem. In ISE Synthesis finished without errors and warnings but when I viewed RTL Schematic there is one component not connected to others. I tried some combinations but nothing helps.
From this unconnected component, counter, I wanted use output value twice, so CNT_VAL was assigned to CNT_VAL_LOC and it was used in DDS and in gen_rect. I thought this is problem so Ive made two counters in this component, what you can see below but it doesn't work too.
Ive designed something and have very big problem. In ISE Synthesis finished without errors and warnings but when I viewed RTL Schematic there is one component not connected to others. I tried some combinations but nothing helps.
From this unconnected component, counter, I wanted use output value twice, so CNT_VAL was assigned to CNT_VAL_LOC and it was used in DDS and in gen_rect. I thought this is problem so Ive made two counters in this component, what you can see below but it doesn't work too.
Code:
entity top_adpll is
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
INPUT : in STD_LOGIC;
OUTPUT : out STD_LOGIC_VECTOR (7 downto 0);
RESET : in STD_LOGIC
--ERROR : out STD_LOGIC
--AF : out STD_LOGIC_VECTOR (7 downto 0)
);
end top_adpll;
architecture Behavioral of top_adpll is
---------------------------Components---------------------------------------------------------------------------
component comparator is
Port ( WE : in STD_LOGIC;
WY : out STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
CE : in STD_LOGIC);
end component;
component JK_ff is
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
RESET : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
component Counter is
Port ( CNT_VAL : out STD_LOGIC_VECTOR (7 downto 0);
CNT_VAL2 : out STD_LOGIC_VECTOR (7 downto 0);
CNT_INC : in STD_LOGIC;
CNT_INC2 : in STD_LOGIC;
CLK : in STD_LOGIC;
CE : in STD_LOGIC;
RESET : in STD_LOGIC);
end component;
component gen_rect is
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
RESET : in STD_LOGIC;
STATE_LENGTH : in STD_LOGIC_VECTOR (7 downto 0);
RECT_VAL : out STD_LOGIC);
end component;
component DDS is
port(
CLK : in std_logic;
CE : in std_logic;
RESET : in std_logic;
PHASE : in std_logic_vector(7 downto 0);
SINE : out std_logic_vector(7 downto 0));
end component;
---------------------------Internal signals---------------------------------------------------------------------------
signal COMP_OUT_LOC : STD_LOGIC := '0';
signal JK_OUT_LOC : STD_LOGIC := '0';
signal CNT_VAL_LOC : STD_LOGIC_VECTOR (7 downto 0) := (others=>'0');
signal CNT_VAL_LOC2 : STD_LOGIC_VECTOR (7 downto 0) := (others=>'0');
signal CLK_LOC : STD_LOGIC := '0';
signal CE_LOC : STD_LOGIC := '0';
signal RESET_LOC : STD_LOGIC := '0';
signal WE_LOC : STD_LOGIC := '0';
signal RECT_VAL_LOC : STD_LOGIC := '0';
begin
--------Inputs--------------------------------------------
CLK_LOC <= CLK;
CE_LOC <= CE;
WE_LOC <= INPUT;
RESET_LOC <= RESET;
kom: comparator port map (CLK=>CLK_LOC, CE=>CE_LOC, RESET=>RESET_LOC, WE=>WE_LOC, WY=>COMP_OUT_LOC);
df: JK_ff port map (CLK=>CLK_LOC, CE=>CE_LOC, RESET=>RESET_LOC, J=>COMP_OUT_LOC, K=>RECT_VAL_LOC, Q=>JK_OUT_LOC);
licz: Counter port map (CLK=>CLK_LOC, CE=>JK_OUT_LOC, RESET=>RESET_LOC, CNT_INC=>'1', CNT_VAL=>CNT_VAL_LOC,CNT_INC2=>'1', CNT_VAL2=>CNT_VAL_LOC2);
gen: gen_rect port map (CLK=>CLK_LOC, CE=>CE_LOC, RESET=>RESET_LOC, RECT_VAL=>RECT_VAL_LOC, STATE_LENGTH=>CNT_VAL_LOC);
dco_dds: DDS port map (CLK=>CLK_LOC, CE=>CE_LOC, RESET=>RESET_LOC, PHASE=>CNT_VAL_LOC2, SINE=>OUTPUT);
end Behavioral;