Ultra Low power design with level shifting 1.8v - 3v

[vinodstanur]

Hi,
I am running an MCU at 1.8v. Another device is connected to 3v because that is the lowest possible voltage for that chip.
My main aim is to achieve the lowest possible power because I am running the system with a 50mAh lipo.

But for interfacing the communication from 3v side to 1.8v side, I can't connect directly coz it will be almost a short for the difference in voltage ie for 3-1.8 = 1.8v
Especially if I am doing some UART or SPI or any handshaking signals from high voltage chip to low voltage chip, as usual it draws a lot of current and can easily damage the pin as well. So I used a level shifter but the problem is the level shifter itself is taking a considerable amount of current in my case and I am not able to achieve a low current in range of few micro amps in low power modes.

My device is running on a BUTTON CELL.

So, I am a bit confused, I would like to know what generally people do in this kind of situation.

If the level shifting is taking power, then the only option for me is to tie the MCU to 3v but the penalty will be a bit more current while the MCU is in RUN mode.

Would like to hear suggestions from experts

 

[KamW]

Some time ago I had similar problem. Finally I have decided to increase volt level for transmision. This solution I have finished on the simulation stage, but I think you could adopt mos level shifter (schematic from google)

with quite high resistor and 1.8 or even 1.2 V transistors it should work with nA.
Of course there will be a lot of power to reload gate, so the transistor parameters are the most important

 

[FvM]

The post #2 MOS level shifter is particularly useful for I2C signals. Standard digital signals use better CMOS gates with level shifting capability. They have effectively zero static power consumption.

 

[vinodstanur]

Hi,
Yes, true the mosfet based level shifter is more suitable for I2C but for high speed SPI etc I feel the 10k pullup will deform the signal badly.

I tried this part for level shifting. It is two directional level shifter.
After checking the internal block diagram I can see two 9k pullups on both sides which may be resulting in the power consumption when my logic levels are low.


Also one more question, will it be a problem or a bit unreliable in a product to connect SPI MOSI(1.8v master) to 3v slave MISO directly without any low to high shifting?
It seems fine for the logic level for high and low looking towards the 3v MISO input pin. But at high speed can this also be a problem?

Because I am planning to keep level shifting only from 3V to 1.8v OUTPUT pins like MISO (slave), IRQ (3v slave > 1.8v MCU) etc.. Does this seems to be a good idea?

Or does it make sense to run MCU at 3v itself to avoid all these issue?

My aim is to achieve a battery life of around 1 or 2 months using a 50mAh battery by designing the most power optimized hardware and then later the firmware.

 

[KlausST]

Hi,

74LVC devices may do the job from 3V3 to 1V8.

They withstand input voltages up to 6.5V even with no supply voltage. So supply it with 1V8.
A 74LVC1G126 draws only 0.1uA signal current as well as supply current.

But there are dedicated level shifter ICs.

What´s the lowest valid signal input high voltage for your 3V3 devices?

Klaus

 

[FvM]

You need to choose level translator specifically for your application circuit. The ST chip is also dedicated for open drain signals, similar to I2C. I would use

3 -> 1.8 V
1.8 V logic gates with 3V compatible inputs (can be driven above VCC), e.g. 74LVC series

1.8 -> 3 V
3V logic gates with asymmetric threshold (LVTTL) like 74 LVT or AUP series.

There are also dedicated level translator ICs with dual supply.

 

[KamW]

Some time ago I have searched and I failed with proper chip solution. I am not sure if you calculated, but your battery will be able to power 74LVC chip (only) for about 4 months...

 

[FvM]

I am not sure if you calculated, but your battery will be able to power 74LVC chip (only) for about 4 months...

I presume you are calculating with datasheet maximum current specifications. That's a pointless way to design low power devices.

 

[asdf44]

Others have given the right answer (purpose built level shifter) but I'll add that I've seen analog muxes effectively used as high->low level shifters. The select line is set to choose between the lower Vcc or GND. As I recall this was used when an unusually low voltage (maybe 1.1) was required to drive an unusually large termination resistor at fairly high speed (maybe 10Mhz). See NLASB3157.