UCF Timing Constraints help

[yakram]

How we can write a setup or hold time constraints for a clock that isn't a global clock, it's come from a combinational logic inside my code ?

Take in mind that the tool gives me an error that the this net isn't connected to a pad or a pin when i type the constraints as shown:

NET "u0_dphy_data_master/the_dphy_master_lp_rx/rx_clk_tmp" TNM_NET = clock;
TIMEGRP "clock" OFFSET = IN 0.2 ns VALID 50 ns BEFORE "u0_dphy_data_master/the_dphy_master_lp_rx/rx_clk_tmp" RISING;

While um reading in the UCF constraints user manual i found that we have to use this commands with a global clocks only

Is my understanding to this point is true or we have another way to define a constraints to a not global clock ?

Thanks in advance

 

[ads_ee]

you should post Xilinx related questions in the FPGA forum...

You need to use a TIMESPEC on the clock e.g.:
TIMESPEC "TS_clock" = PERIOD "clock" 50.00 ns HIGH 50 %;

and change your OFFSET constraint so it uses the TNM_NET clock as the clock name.
NET "SOME_INPUT_PIN" OFFSET = IN 0.2 ns VALID 50 ns BEFORE "clock" RISING;

**broken link removed**