Two questions regarding to HDL design

[sgokhan]

1- Is it wiser to develop a design using mixed style (HDL + Schematics)

2-Which tool supports a general design environment (including simulation) for that kind of designs?

Thanks.

 

[echo47]

Here are two past discussions about HDL vs schematic. You can search for more.



Most designers abandoned schematics long ago.

 

[m.abdulmoniem]

We rarely use the schematic design entry
if you need a gerneralized environment use FPGADV from mentor graphics
it contains HDS, Modelsim, and Leonardo or Precission
Also you can invok the PAR tool from it and directly download your configuration binary file onto the FPGA

Thanks

 

[it_boy]

I think Xilinx ISE latest versions should support mixed language designs including simulations

 

[sgokhan]

I think Xilinx ISE latest versions should support mixed language designs including simulations

Do you mean VHDL + Verilog entry using the term "mixed language"?

 

[it_boy]

I think Xilinx ISE latest versions should support mixed language designs including simulations

Do you mean VHDL + Verilog entry using the term "mixed language"?

Yes. It definitely supports VHDL + verilog. As far as I remember there were some constraints thouugh, like the top module should be VHDL etc.

I have not tried VHDL + Veriog + Schematics, but I think the tool may support. Maybe you can try once in the free webpack (If you dont have ISE).

 

[RegUser_2]

Aldec Active HDL is an example of tool which supports Schematic entry, VHDL, Verilog, Abel, SystemC and have built in simulator.

Another one is the Dolphin Smash, which supports VHDL-AMS, Verilog-AMS, SystemC, SPICE and is used for simulation.

 

[sgokhan]

What I have understood from your postings and a few web-searches, FPGA vendors have their own tools, which support mixed language design including schematics. I am assuming the schematic integrated designs are for beginners or to make easier the design job.

I used Smash while I was pacing for a DAC projects. Though, we had only used VHDL-AMS. In addition to that, I know that it supports variety HDL languages. Yet the only supply dry simulation environment.

How the tools differ when it comes to the ASIC domain? I mean even a simple IC contains thousands of transistors. Don't they use graphical simulators to evaluate the design instead of dry HDL coding?

 

[RegUser_2]

What I have understood from your postings and a few web-searches, FPGA vendors have their own tools, which support mixed language design including schematics. I am assuming the schematic integrated designs are for beginners or to make easier the design job.

I used Smash while I was pacing for a DAC projects. Though, we had only used VHDL-AMS. In addition to that, I know that it supports variety HDL languages. Yet the only supply dry simulation environment.

How the tools differ when it comes to the ASIC domain? I mean even a simple IC contains thousands of transistors. Don't they use graphical simulators to evaluate the design instead of dry HDL coding?

The whole point of the HDL is to use higher level of abstraction, so the actual silicon layout becomes a problem for the synthesis tool. Naturally for successfull synthesis some have to follow RTL coding guidelines, and for specific vendor to instantiate modules optimized by this vendor.

And basicly for small designs, any combination of visual aids is very helpfull. Various tools allaw vide combination of visual aids (defining graphical block diagrams and interconections of modules at the top level of the design, truth tables, controll flow graphs, grapical state machines).

Pick an FPGA vendor you feel you like and fetch yourself some demo development tools to futs around on some small project (for instance Lattice ispLEVER contains nice set of design entry tool, two synthesis tools (Synplicity and Precision RTL) and the industry standart Modelsim similation tool)

 

[funster]

it's best to use hdl to develop a design, that's the current direction.

1- Is it wiser to develop a design using mixed style (HDL + Schematics)

2-Which tool supports a general design environment (including simulation) for that kind of designs?

Thanks.

 

[arnoud]

I strongly suggest to use only vhdl or verilog, no grapical entry.
The graphics can not easily ported over to other compilers.
Sadly making top level design on larger fpga is a very long task, but for that there are some scripts available to help you out.

 

[VHDL_Verilog_user]

Yeah, it is wiser.
I think whether u use HDL or Grapical entry depends on the situation. For example, just a few devices composed the circuit using the Grapical entry is fittable, and some very complex circuit using HDLs are much better.

I recommone u to try Quartus2.

 

[zeeshanzia84]

It's better and more manageable if you do the entire design using HDL (either verilog or VHDL)....leave the schematic entry to junior students learning the basics of digital design.

Try Xilinx ISE 9.