Transistor selection in switched capacitor DC DC converter

[gkkrish52]

Efficiency Estimation of Switched Capacitor DC DC Converter

Hi. I am new to Switched capacitor DC DC Converters. I need a little help in finding the efficiency of the converter. The specs of the circuit as follows.

Vin = 1 V, Vout = 0.5 V, Conversion Ratio = 1/2, Load currrent = 10 mA, C fly, C Load = 20 pF. Frequency = 1.73 GHz.

Efficiency = Pout/Pin. How to calculate Pout and Pin. I am using a dc supply for input, and clocks.

Attached the circuit for reference. Kindly help in how to calculate the efficiency.


Thanks in advance. Have a good day.

Best ,
Gopal

 

[FvM]

Re: Efficiency Estimation of Switched Capacitor DC DC Converter

Pout is 0.5V*10mA, apparently. Pin has to measured in simulation. Seriously it should include the gate driver power consumption.

The efficiency is determined by transistor capacitances and rdson. In would be 100 % with ideal transistors (cx = 0, rdson = 0). In practice it's probably rather low, depending on the available transistor technology. Scaling the transistor sizes for maximal efficiency is your main design job.

 

[gkkrish52]

Re: Efficiency Estimation of Switched Capacitor DC DC Converter

Dear FvM,

I am using 40 nm technology. Pin has to be found by measuring the current from the supply voltage. Kindly correct me if am wrong. I have calulated the rdson for nmos transistor using dc analysis. I have found the gate cap using the transient analysis. How to calculate the gate driver power consumption? I have connected the input supply to the source of the transistors. I have used NMOS on discharging path and PMOS on charging path.
Thanks for your kind help.

 

[FvM]

Re: Efficiency Estimation of Switched Capacitor DC DC Converter

I think you can operate the circuit in a transient simulation until steady state is reached and measure Pin. Suitable initial conditions, e.g. charged output capacitor can reduce the simulation time.

 

[gkkrish52]

Transistor selection in switched capacitor dc dc converter

Hi All. I am trying to build a switched capacitor dc dc 1/2 converter with complementary clocks. I following the topology mentioned below.

I am using PMOS in charge path and NMOS in charge path. Kindly advice me on this selection of nmos and pmos in charge and discharge path. Thanks in advance. Have a nice day.