Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
For standard I/O pins the minimum trace width depends on the maximum current output requirements of your design, but even you selecting the smaller thickness (0,5Oz) in high temperature conditions, would result in a trace width smaller than that PCB manufacturer would be able to deal. In shorts, even you defining the trace width and spacing equal to the pinout itself, this would not become a problem at all.
You should check which technology is supported by your preferred PCB supplier. 150 µm minimal structure size (both trace width and spacing) is a standard these days, 125 µm is available from some manufacturers without extra costs, 100 µm usually with surcharge.
I believe that the TQFP-64 package can be well connected with 150 µm standard technology, preferably on a 4-layer board with ground plane.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
