Timing diagram generation for IC testing

[adix]

Dear all,
I designed an IC chip. I am preparing the test setup at the moment. The difficult task will be the generation of patterns to control all the functions of the chip. I need more then 30 different control signals (syncronised to the main clock). I have an FPGA board. Can anybody tell me if there are any tutorials explaining how to generete patterns to test ICs with a FPGA? Sorry for this question but I am a beginner in the field.

 

[erikl]

This depends very much on which signal generators and which measurement equipment you can dispose of, and in which form you are able to describe your test patterns (manually or high level language, like Verilog or VHDL, s. e.g. -- as an example -- this thread.