Timing closure is the solution?

[shakeebh]

HI ppl

I am trying to integrate my smaller modules together to complete my design. The problem is that my post layout results of each module is fine as long as I test them individually. But when I integrate them with each other into a system, they start acting crazy. I tried to relax clock speed and everything of the sorts but it just doesn't seem to be working with anything. It's as if my state machine's logic inference has changed or something. Can anyone tell me what should I do to ensure that my modules produce the same result exactly as they do individually even after I put them together? Will I have to do some kind of timing closure of my modules before integrating them? If yes, how? And if not, then what?

Thanking you in anticipation

 

[SkyHigh]

I presume your smaller modules at high abstraction level (in Verilog) are actually cores generated in the layout. Putting many cores together, you have to consider many factors to make it work fine.

1. Make sure you set your layout tool to generate a global clock symmetrical to all the cores, so they have a common clock source for synchronous state machine. Not doing so, you will put your cores working in an asynchronous state, if this is something that you wanted, but I presume not.

Although within a core, you have a local domain clock, but this clock still derives its clock source from the global clock. You might want to add a prescalar if required.

2. The buses between cores must be set to be global wires in the layout tool. The layout tool will add drivers or multi-stage buffers to shorten the transition time between logic 1 and 0.


If the above doesn't work for putting all cores together, then you can try this:

1. Copy all the HDL sources (in Verilog or VHDL) and put them all into one source file. It might easier for Verilog, but for VHDL, you need to carefully include the necessary standard libraries, work libraries and etc and use components when needed.

2. Compile and simulate. Check the functionality.

3. Synthesis and run STA. Check for timing violation.

4. Floorplann, place and route. Run post-layout sim. Check for timing violation again. If you want, check for parastics and power consumption if you want to.

Goodluck!

 

[shakeebh]

thanks a lot skyhigh for that reply. but i am afraid that my problem doesnt solve here.

Actually I am getting this problem while trying to integrate asynchronous state machine modules. I will be precise now. I wrote a code of one module (of asynch state machine), tested it individually and it appeared to be working just fine for all test conditions. and this is post layout simulation....now i put it inside another module - another aynch fsm - which i had tested before to be working perfect through to the timing simulation. However now when i try to see the combined results of these two modules, i see strange behavior. I find my state machines changing states anomalously, even though all inputs are stable and as far as my code goes, there aren't any race conditions or something (I do state assignments manually). after all, the modules were generating results par behavioral simulation earlier on. so now could u tell me what is going wrong here? could it be that my synthesis tool is doing some incorrect logic synthesis or making incorrect state assignments which you would know how vital is for asynchronous state machines.

In addition could you refer to me some good tutorials that illustrate how I could do all the necessary things u mentioned in ur earlier post? will really appreciate it

thanks again