flyjuju2
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Hi !
I'm currently performing an implementation on an FPGA with Quartus II and I have a problem with timing analysis relating to setup time, hold time and negative slack. I would have liked to know CONCRETELY what actions I have to take in order to solve this because I know absolutely nothing about STA.
Thanks a lot !!!
I'm currently performing an implementation on an FPGA with Quartus II and I have a problem with timing analysis relating to setup time, hold time and negative slack. I would have liked to know CONCRETELY what actions I have to take in order to solve this because I know absolutely nothing about STA.
Thanks a lot !!!