Timer MC14541B wrong delay

[TXRX]

Hi,
I buit the attached timer and receive a delay of 604mSec instead of 640mSec, How can you explain ?
n=13

2^(n-1)=4096

VCC=+16VDC
The mesurement of the Delay is between VCC start up to change state at the OUTPUT.
Thanks,

 

[danadakk]

Datasheet has no specs on accuracy for RC based delays. Or delay from power up. Then
there is the tolerance of the RC components used that affects timing.

If you need specific pulse width, latency, accuracy this is not the way to achieve this.

What specs, functionality are you trying to achieve ?


Regards, Dana.

 

[TXRX]

The tolerance of the resistor and capacitor are 1%, but the time difference is very large.
I do not need a accurate timer, i want to understand why there is large deviation.

 

[danadakk]

These CMOS gate based RC oscillators are notorious for lousy timing
accuracy, thats why there is no spec, for a .000000000000000001%
accurate R & C. There even is no jitter spec at all due to noise.

There is huge variation chip to chip in MOSFET gate Vth.

Regards, Dana.

 

[TXRX]

Hi Dana,
Do i receive shorter time because the Vth is low ?
Regards,

 

[FvM]

Are you sure that the datasheet specifies reproducible timing behaviour after Vcc startup?

 

[TXRX]

There is no data on reproducible timing behaviour.
I built 4 identical circuits and measure and receive: 604.23 , 603.39 , 608.99 , 607.3mSec.
The average value is far from calculate delay: 640mSec.

 

[danadakk]

Hi Dana,
Do i receive shorter time because the Vth is low ?
Regards,

Would have to simulate it to answer, or bench test.

Regards, Dana.

 

[FvM]

There is no data on reproducible timing behaviour.
I built 4 identical circuits and measure and receive: 604.23 , 603.39 , 608.99 , 607.3mSec.
The average value is far from calculate delay: 640mSec.

I'm not asking about low percent deviation. The question is, if the monoflop is correctly initialized when the pulse starts immediately with Vcc startup? Does the datasheet specify?

 

[d123]

Hi,

Without reading datasheet, besides unavoidable randomness of IC parts and passives (measure R and C where possible for certainty and check cap datasheet for actual capacitance, at xVoltage, xFrequency, xTemperature) might be that timing capacitor needs to be charged or discharged to some degree or other for pulse to be correct length; like 555 astable after reset or first pulse is longer as capacitor is discharged so has to go from 0V to 2/3rds Vcc when normal operation is only from 1/3rd to 2/3rds. If so, might be able to add start-up helper circuit for predictable consistent timing with just passives, if such thing needed at all.

 

[Easy peasy]

The oscillator will vary with Vcc too - best performance at 15V

--- Updated Jul 5, 2022 ---

unless you have very high quality NPO cap - it will almost certainly be a little lower in value than that supposedly supplied - hence higher freq hence shorter time.

 

[danadakk]

At no time have you stated you actual design goals, probably a good time
to do that before Forum tries to help further.

1) Delay accuracy desired, and speced from what event to the next.
2) Allowable T and V specs.
3) If you care about jitter spec for that.

To name a few.

Regards, Dana.