Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In deep sub micron processes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. The suggestion from foundry is to use tie cells for this purpose. These cells are part of standard-cell library. The cells which require Vdd, comes and connect to Tie high...(so tie high is a power supply cell)...while the cells which wants Vss connects itself to Tie-low
I am unable to understand this statement
So if a gate has to turn on only on VDD it must be brought near Pcells. This is called Tie_high ???
wts this Pcells and Ncells
Tie-hi and Tie-low is usually provided as a standard cell. If not, you can opt to make one yourself.
The reason these exist is to provide some kind of shielding for the logic 1 and logic 0 metal lines. Tying these nets directly to VDD and GND can cause various issues (as others noted, ground bouncing). It's not necessary in many cases if you trust your regulator and/or your design is sufficiently small that there isn't that much coupling capacitance on your ground line but it's usually a good idea.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.