Leep
Junior Member level 3
I'm working through the book FPGA Prototyping By Verilog Examples (by Pong P. Chu) and I've had no problems up until the end of chapter 3 with the fp_adder example. I'm getting warnings that I can't figure out (I've even synthesized directly from the .v files for the chapter from the book's website, with my .ucf file [the book is for different board, pins are different]). The warnings I'm getting are during Place & Route:
WARNINGar:288 - The signal sw<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNINGar:288 - The signal sw<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNINGar:288 - The signal sw<4>_IBUF has no load. PAR will not attempt to route this signal.
WARNINGar:283 - There are 3 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
The source is below. I included disp_mux.v and hex_to_sseg.v for completeness, but I've used those in several other projects and they seem to be working fine (simple controller for 4-digit seven-segment display with common anode).
fp_adder_test.v
fp_adder.v
disp_mux.v
hex_to_sseg.v
fp_adder_test.ucf
The target board is a Digilent Nexys 3 with a Xilinx Spartan-6 FPGA. Has anyone else worked through the book FPGA Prototyping By Verilog Examples (by Pong P. Chu) and had similar problems? If anyone could look at the source and see if you spot something obvious that I'm missing, or if you have a Nexys 3 if you could try to synthesize it to the board and see if you get the same warnings, I'd greatly appreciate it! Thanks!
WARNINGar:288 - The signal sw<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNINGar:288 - The signal sw<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNINGar:288 - The signal sw<4>_IBUF has no load. PAR will not attempt to route this signal.
WARNINGar:283 - There are 3 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
The source is below. I included disp_mux.v and hex_to_sseg.v for completeness, but I've used those in several other projects and they seem to be working fine (simple controller for 4-digit seven-segment display with common anode).
fp_adder_test.v
Code:
module fp_adder_test
(
input wire clk,
input wire [1:0] btn,
input wire [7:0] sw,
output wire [3:0] an,
output wire [7:0] sseg
);
wire sign1, sign2, sign_out;
wire [3:0] exp1, exp2, exp_out;
wire [7:0] frac1, frac2, frac_out;
wire [7:0] led3, led2, led1, led0;
assign sign1 = 1'b0;
assign exp1 = 4'b1000;
assign frac1 = {1'b1, sw[1:0], 5'b10101};
assign sign2 = sw[7];
assign exp2 = btn;
assign frac2 = {1'b1, sw[6:0]};
fp_adder fp_unit
(
.sign1(sign1), .sign2(sign2), .exp1(exp1), .exp2(exp2),
.frac1(frac1), .frac2(frac2), .sign_out(sign_out),
.exp_out(exp_out),.frac_out(frac_out)
);
hex_to_sseg sseg_unit_0
(
.hex(exp_out), .dp(1'b0), .sseg(led0)
);
hex_to_sseg sseg_unit_1
(
.hex(frac_out[3:0]), .dp(1'b1), .sseg(led1)
);
hex_to_sseg sseg_unit_2
(
.hex(frac_out[7:4]), .dp(1'b0), .sseg(led2)
);
assign led3 = (sign_out) ? 8'b11111110 : 8'b11111111;
disp_mux disp_unit
(
.clk(clk), .reset(1'b0), .in0(led0), .in1(led1),
.in2(led2), .in3(led3), .an(an), .sseg(sseg)
);
endmodule
fp_adder.v
Code:
module fp_adder
(
input wire sign1, sign2,
input wire [3:0] exp1, exp2,
input wire [7:0] frac1, frac2,
output reg sign_out,
output reg [3:0] exp_out,
output reg [7:0] frac_out
);
reg signb, signs;
reg [3:0] expb, exps, expn, exp_diff;
reg [7:0] fracb, fracs, fraca, fracn, sum_norm;
reg [8:0] sum;
reg [2:0] lead0;
always @*
begin
// Stage 1 - Sort
if ({exp1, frac1} > {exp2, frac2})
begin
signb = sign1;
signs = sign2;
expb = exp1;
exps = exp2;
fracb = frac1;
fracs = frac2;
end
else
begin
signb = sign2;
signs = sign1;
expb = exp2;
exps = exp1;
fracb = frac2;
fracs = frac1;
end
// Stage 2 - Align
exp_diff = expb - exps;
fraca = fracs >> exp_diff;
// Stage 3 - Result of Add/Subtract
if (signb == signs)
begin
sum = {1'b0, fracb} + {1'b0, fraca};
end
else
begin
sum = {1'b0, fracb} - {1'b0, fraca};
end
// Stage 4 - Normalize
if (sum[7])
lead0 = 3'o0;
else if (sum[6])
lead0 = 3'o1;
else if (sum[5])
lead0 = 3'o2;
else if (sum[4])
lead0 = 3'o3;
else if (sum[3])
lead0 = 3'o4;
else if (sum[2])
lead0 = 3'o5;
else if (sum[1])
lead0 = 3'o6;
else
lead0 = 3'o7;
sum_norm = sum << lead0;
if(sum[8]) // carry out
begin
expn = expb + 1;
fracn = sum[8:1];
end
else if (lead0 > expb) // too small to normalize
begin
expn = 0;
fracn = 0;
end
else
begin
expn = expb - lead0;
fracn = sum_norm;
end
// Stage 5 - Form output
sign_out = signb;
exp_out = expn;
frac_out = fracn;
end
endmodule
disp_mux.v
Code:
module disp_mux
(
input wire clk, reset,
input [7:0] in3, in2, in1, in0,
output reg [3:0] an, // enable, 1-out-of-4 asserted low
output reg [7:0] sseg // led segments
);
// constant declaration
// refreshing rate around 800 Hz (100 MHz/2^17)
localparam N = 19;
// signal declaration
reg [N-1:0] q_reg;
wire [N-1:0] q_next;
// N-bit counter
// register
always @(posedge clk, posedge reset)
if (reset)
q_reg <= 0;
else
q_reg <= q_next;
// next-state logic
assign q_next = q_reg + 1;
// 2 MSBs of counter to control 4-to-1 multiplexing
// and to generate active-low enable signal
always @*
case (q_reg[N-1:N-2])
2'b00:
begin
an = 4'b1110;
sseg = in0;
end
2'b01:
begin
an = 4'b1101;
sseg = in1;
end
2'b10:
begin
an = 4'b1011;
sseg = in2;
end
default:
begin
an = 4'b0111;
sseg = in3;
end
endcase
endmodule
hex_to_sseg.v
Code:
module hex_to_sseg
(
input wire [3:0] hex,
input wire dp,
output reg [7:0] sseg
);
always @*
begin
case (hex)
4'h0: sseg[6:0] = 7'b0000001;
4'h1: sseg[6:0] = 7'b1001111;
4'h2: sseg[6:0] = 7'b0010010;
4'h3: sseg[6:0] = 7'b0000110;
4'h4: sseg[6:0] = 7'b1001100;
4'h5: sseg[6:0] = 7'b0100100;
4'h6: sseg[6:0] = 7'b0100000;
4'h7: sseg[6:0] = 7'b0001111;
4'h8: sseg[6:0] = 7'b0000000;
4'h9: sseg[6:0] = 7'b0000100;
4'ha: sseg[6:0] = 7'b0000010;
4'hb: sseg[6:0] = 7'b1100000;
4'hc: sseg[6:0] = 7'b1110010;
4'hd: sseg[6:0] = 7'b1000010;
4'he: sseg[6:0] = 7'b0010000;
default: sseg[6:0] = 7'b0111000;
endcase
sseg[7] = dp;
end
endmodule
fp_adder_test.ucf
Code:
Net "clk" LOC=V10;
Net "sseg<6>" LOC = T17;
Net "sseg<5>" LOC = T18;
Net "sseg<4>" LOC = U17;
Net "sseg<3>" LOC = U18;
Net "sseg<2>" LOC = M14;
Net "sseg<1>" LOC = N14;
Net "sseg<0>" LOC = L14;
Net "sseg<7>" LOC = M13;
Net "an<0>" LOC = N16;
Net "an<1>" LOC = N15;
Net "an<2>" LOC = P18;
Net "an<3>" LOC = P17;
Net "sw<0>" LOC = T10;
Net "sw<1>" LOC = T9;
Net "sw<2>" LOC = V9;
Net "sw<3>" LOC = M8;
Net "sw<4>" LOC = N8;
Net "sw<5>" LOC = U8;
Net "sw<6>" LOC = V8;
Net "sw<7>" LOC = T5;
Net "btn<1>" LOC = B8;
Net "btn<0>" LOC = D9;
The target board is a Digilent Nexys 3 with a Xilinx Spartan-6 FPGA. Has anyone else worked through the book FPGA Prototyping By Verilog Examples (by Pong P. Chu) and had similar problems? If anyone could look at the source and see if you spot something obvious that I'm missing, or if you have a Nexys 3 if you could try to synthesize it to the board and see if you get the same warnings, I'd greatly appreciate it! Thanks!