The CML output buffer problem with silicon test

[John Xu]

cml output

Our design has the CML output buffer, before it is the amplifier stage. In design, we considered teh mismatch of the amp satge and CML stage and found no issues on the duty cycles for the output eye-diagram even with the output offset up to 200mV. But for the silicon test, we found the duty cycles degrade for the output offset is up to 50mV. Why so big descrepancy!!??

Can anyone help to explain it?

 

[suria3]

what is a cml output?

CML buffer has the 50ohm load resistor to vdd. The mismatch of this resistor during the fabrication could have contributed the offset as the 50ohm value tend to give large variation. Did you run mismatch analysis in the morle carlo analysis and what was your pass percentage. If you got a 80% pass, that will more guarantee your design to work in silicon. There is also a chances that the offset come along from the previos amplifier stages and it is amplified until 50mV. Here it is more to random offset due to mismatch compared to your systematic offset from your simulation level which you couldn't see much on them.

 

[chang830]

Re: the CML output buffer

the qustion here is that the obvious descrepancy between the simulation and measurement.The design showed that it can tolerate up to ~200mV output dc offsaet while the 80mV dc output offset will induce obvios PWD with the same input.Afetr checking, the test condition and simulation condition is same.Can any explain it?

 

[neoflash]

the CML output buffer

do you have data of how much duty-cycle distorted?