The clock of DDR Memory Modules

[lvwx]

I want to control 3 DDR Memory Modules by FPGA ,but i wonder how can i deal with the clock of these Memory Modules.Connect them together to FPGA or connect them one by one to FPGA?And does them neeed any Match resistance?

 

[Aoxomox]

have a look at the JEDEC standard for DDR DIMM.
e.g.
https://www.intel.com/technology/memory/pcsdram/spec/ddr_unbuff_dimm_spec_09.pdf

On each memory module the clockline is wired to each chip. so when having 8 ic's per module you have to drive 8 times the capacity of this pin. when connecting 3 modules ... it's 24 pins with 266MHz or even more. you should think of separatly supplying the modules. Matching resistances are necessary. ( in Jedec standard those lines have 10 ohms in series).

More critically than the resistance is the wirelength of the clocksignal. all wires to one module should have almost the same length. probably it's good to lengthen then clockline a bit so that all other signals are stable when the pulse on this line occurs.