tested output of delay locked loop in cadence spectre tool in .18um technology.

[udaykumar25]

hi,


I am doing a project on delay locked loop.In that i had a doubt that i tested the delay locked loop the output is like this.but in that result the ref clk and output of vcdl wont be locked exactly.can u suggest any idea where it went wrong .


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how to calculate the jitter and power consumption in cadence spectre tool(virtuoso).

 

[Vigneshrajaece]

Hi,

I am also working on delay locked loops.. I too have the same problem ... my output is not locking with my input signal..
To measure power, in the ADE window select outputs -> save all... In the window appears0, enable the check box all in power in subcircuits ..

Then run the simulation... then go for tools -> results browser.... Then select tran-tran in the waveform window... then from the available list of signals, select pwr( will be in red colour) right click on it select append...

the power consumption waveform will appear.. select it .. right click on it and select calculator..
in the calculator , select the average function and select evaluate buffer... This will give the average power consumption of the circuit..

Hope this is crct..

 

[D.A.(Tony)Stewart]

Rising edge is locked but output is asymmetric, at the top where current is low. Can you correct this?

 

[Vigneshrajaece]

Hi...

i cant sort out what the problem is from the waveforms ... can u send me the schematics of the components of DLL so that i can sort out what the problem is... ?

 

[Vigneshrajaece]

This is the phase detector , CP , VCDL output of my DLL..

 

[tompham]

Hi
You should use 50% duty circle output buffer to get good result. The circuit is simple and can find from google